^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This driver is heavily based upon:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Portions Copyright (C) 2001 Sun Microsystems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Portions Copyright (C) 2003 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Look into engine reset on timeout errors. Should not be required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRV_NAME "pata_hpt37x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRV_VERSION "0.6.23"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct hpt_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 xfer_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct hpt_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct hpt_clock const *clocks[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* key for bus clock timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * cycles = value + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * cycles = value + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 28 UDMA enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 29 DMA enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 30 PIO_MST enable. If set, the chip is in bus master mode during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * PIO xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 31 FIFO enable. Only for PIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct hpt_clock hpt37x_timings_33[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { XFER_UDMA_5, 0x12446231 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { XFER_UDMA_4, 0x12446231 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { XFER_UDMA_3, 0x126c6231 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { XFER_UDMA_2, 0x12486231 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { XFER_UDMA_1, 0x124c6233 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { XFER_UDMA_0, 0x12506297 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { XFER_MW_DMA_2, 0x22406c31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { XFER_MW_DMA_1, 0x22406c33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { XFER_MW_DMA_0, 0x22406c97 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { XFER_PIO_4, 0x06414e31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { XFER_PIO_3, 0x06414e42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { XFER_PIO_2, 0x06414e53 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { XFER_PIO_1, 0x06814e93 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { XFER_PIO_0, 0x06814ea7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct hpt_clock hpt37x_timings_50[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { XFER_UDMA_6, 0x12848242 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { XFER_UDMA_5, 0x12848242 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { XFER_UDMA_4, 0x12ac8242 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { XFER_UDMA_3, 0x128c8242 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { XFER_UDMA_2, 0x120c8242 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { XFER_UDMA_1, 0x12148254 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { XFER_UDMA_0, 0x121882ea },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { XFER_MW_DMA_2, 0x22808242 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { XFER_MW_DMA_1, 0x22808254 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { XFER_MW_DMA_0, 0x228082ea },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { XFER_PIO_4, 0x0a81f442 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { XFER_PIO_3, 0x0a81f443 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { XFER_PIO_2, 0x0a81f454 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { XFER_PIO_1, 0x0ac1f465 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { XFER_PIO_0, 0x0ac1f48a }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct hpt_clock hpt37x_timings_66[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { XFER_UDMA_6, 0x1c869c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { XFER_UDMA_4, 0x1c8a9c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { XFER_UDMA_3, 0x1c8e9c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { XFER_UDMA_2, 0x1c929c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { XFER_UDMA_1, 0x1c9a9c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { XFER_UDMA_0, 0x1c829c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { XFER_MW_DMA_2, 0x2c829c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { XFER_MW_DMA_1, 0x2c829c66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { XFER_MW_DMA_0, 0x2c829d2e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { XFER_PIO_4, 0x0c829c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { XFER_PIO_3, 0x0c829c84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { XFER_PIO_2, 0x0c829ca6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { XFER_PIO_1, 0x0d029d26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { XFER_PIO_0, 0x0d029d5e }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct hpt_chip hpt370 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "HPT370",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) hpt37x_timings_33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct hpt_chip hpt370a = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "HPT370A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) hpt37x_timings_33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) hpt37x_timings_50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct hpt_chip hpt372 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "HPT372",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) hpt37x_timings_33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) hpt37x_timings_50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) hpt37x_timings_66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct hpt_chip hpt302 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "HPT302",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) hpt37x_timings_33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) hpt37x_timings_50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) hpt37x_timings_66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct hpt_chip hpt371 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "HPT371",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) hpt37x_timings_33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) hpt37x_timings_50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) hpt37x_timings_66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct hpt_chip hpt372a = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "HPT372A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) hpt37x_timings_33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) hpt37x_timings_50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) hpt37x_timings_66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct hpt_chip hpt374 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "HPT374",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) hpt37x_timings_33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * hpt37x_find_mode - reset the hpt37x bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @speed: transfer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Return the 32bit register programming information for this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * that matches the speed provided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct hpt_clock *clocks = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) while (clocks->xfer_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (clocks->xfer_speed == speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return clocks->timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0xffffffffU; /* silence compiler warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const char * const list[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned char model_num[ATA_ID_PROD_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) i = match_string(list, -1, model_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pr_warn("%s is not supported for %s\n", modestr, list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const char * const bad_ata33[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "Maxtor 90845U3", "Maxtor 90650U2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "Maxtor 90510D4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const char * const bad_ata100_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "IBM-DTLA-307075",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "IBM-DTLA-307060",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "IBM-DTLA-307045",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "IBM-DTLA-307030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "IBM-DTLA-307020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "IBM-DTLA-307015",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "IBM-DTLA-305040",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "IBM-DTLA-305030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "IBM-DTLA-305020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "IC35L010AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "IC35L020AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "IC35L030AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "IC35L040AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "IC35L060AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "WDC AC310200R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * hpt370_filter - mode selection filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Block UDMA on devices that cause trouble with this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (adev->class == ATA_DEV_ATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mask &= ~ATA_MASK_UDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mask &= ~(0xE0 << ATA_SHIFT_UDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * hpt370a_filter - mode selection filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Block UDMA on devices that cause trouble with this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (adev->class == ATA_DEV_ATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mask &= ~(0xE0 << ATA_SHIFT_UDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * hpt372_filter - mode selection filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @mask: mode mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * The Marvell bridge chips used on the HighPoint SATA cards do not seem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ata_id_is_sata(adev->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * hpt37x_cable_detect - Detect the cable type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * @ap: ATA port to detect on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Return the cable type attached to this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int hpt37x_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 scr2, ata66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pci_read_config_byte(pdev, 0x5B, &scr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) udelay(10); /* debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Cable register now active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pci_read_config_byte(pdev, 0x5A, &ata66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Restore state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pci_write_config_byte(pdev, 0x5B, scr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ata66 & (2 >> ap->port_no))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * hpt374_fn1_cable_detect - Detect the cable type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @ap: ATA port to detect on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Return the cable type attached to this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int hpt374_fn1_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int mcrbase = 0x50 + 4 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u16 mcr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 ata66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Do the extra channel work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pci_read_config_word(pdev, mcrbase + 2, &mcr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Set bit 15 of 0x52 to enable TCBLID as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pci_read_config_byte(pdev, 0x5A, &ata66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Reset TCBLID/FCBLID to output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pci_write_config_word(pdev, mcrbase + 2, mcr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ata66 & (2 >> ap->port_no))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * hpt37x_pre_reset - reset the hpt37x bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * @link: ATA link to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Perform the initial reset handling for the HPT37x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct pci_bits hpt37x_enable_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 0x50, 1, 0x04, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0x54, 1, 0x04, 0x04 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Reset the state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 addr1, addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 reg, timing, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u8 fast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) addr2 = 0x51 + 4 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Fast interrupt prediction disable, hold off interrupt disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pci_read_config_byte(pdev, addr2, &fast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) fast &= ~0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) fast |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pci_write_config_byte(pdev, addr2, fast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Determine timing mask and find matching mode entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (mode < XFER_MW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mask = 0xcfc3ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) else if (mode < XFER_UDMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mask = 0x31c001ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mask = 0x303c0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) timing = hpt37x_find_mode(ap, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pci_read_config_dword(pdev, addr1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) reg = (reg & ~mask) | (timing & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pci_write_config_dword(pdev, addr1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * hpt370_set_piomode - PIO setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * @adev: device on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * Perform PIO mode setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hpt370_set_mode(ap, adev, adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * hpt370_set_dmamode - DMA timing setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * @adev: Device being configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Set up the channel for MWDMA or UDMA modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) hpt370_set_mode(ap, adev, adev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * hpt370_bmdma_end - DMA engine stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * @qc: ATA command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * Work around the HPT370 DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) void __iomem *bmdma = ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u8 dma_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (dma_stat & ATA_DMA_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (dma_stat & ATA_DMA_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Clear the engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Stop DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Clear Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) bmdma + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Clear the engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ata_bmdma_stop(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 addr1, addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 reg, timing, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u8 fast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) addr2 = 0x51 + 4 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Fast interrupt prediction disable, hold off interrupt disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pci_read_config_byte(pdev, addr2, &fast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) fast &= ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pci_write_config_byte(pdev, addr2, fast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Determine timing mask and find matching mode entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (mode < XFER_MW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) mask = 0xcfc3ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) else if (mode < XFER_UDMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mask = 0x31c001ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mask = 0x303c0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) timing = hpt37x_find_mode(ap, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pci_read_config_dword(pdev, addr1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) reg = (reg & ~mask) | (timing & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pci_write_config_dword(pdev, addr1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * hpt372_set_piomode - PIO setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * @adev: device on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * Perform PIO mode setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) hpt372_set_mode(ap, adev, adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * hpt372_set_dmamode - DMA timing setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * @adev: Device being configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * Set up the channel for MWDMA or UDMA modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hpt372_set_mode(ap, adev, adev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * hpt37x_bmdma_end - DMA engine stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * @qc: ATA command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * Clean up after the HPT372 and later DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int mscreg = 0x50 + 4 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u8 bwsr_stat, msc_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pci_read_config_byte(pdev, mscreg, &msc_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (bwsr_stat & (1 << ap->port_no))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ata_bmdma_stop(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static struct scsi_host_template hpt37x_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * Configuration for HPT370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct ata_port_operations hpt370_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .bmdma_stop = hpt370_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .mode_filter = hpt370_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .cable_detect = hpt37x_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .set_piomode = hpt370_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .set_dmamode = hpt370_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .prereset = hpt37x_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * Configuration for HPT370A. Close to 370 but less filters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static struct ata_port_operations hpt370a_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .inherits = &hpt370_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .mode_filter = hpt370a_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Configuration for HPT371 and HPT302. Slightly different PIO and DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * mode setting functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static struct ata_port_operations hpt302_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .bmdma_stop = hpt37x_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .cable_detect = hpt37x_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .set_piomode = hpt372_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .set_dmamode = hpt372_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .prereset = hpt37x_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * Configuration for HPT372. Mode setting works like 371 and 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * but we have a mode filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static struct ata_port_operations hpt372_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .inherits = &hpt302_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .mode_filter = hpt372_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * Configuration for HPT374. Mode setting and filtering works like 372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * but we have a different cable detection procedure for function 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static struct ata_port_operations hpt374_fn1_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .inherits = &hpt372_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .cable_detect = hpt374_fn1_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * hpt37x_clock_slot - Turn timing to PC clock entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * @freq: Reported frequency timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * @base: Base timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * and 3 for 66Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned int f = (base * freq) / 192; /* Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (f < 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0; /* 33Mhz slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (f < 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return 1; /* 40Mhz slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (f < 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 2; /* 50Mhz slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 3; /* 60Mhz slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * hpt37x_calibrate_dpll - Calibrate the DPLL loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * succeeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int hpt37x_calibrate_dpll(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 reg5b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 reg5c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) for (tries = 0; tries < 0x5000; tries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pci_read_config_byte(dev, 0x5b, ®5b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (reg5b & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* See if it stays set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) for (tries = 0; tries < 0x1000; tries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pci_read_config_byte(dev, 0x5b, ®5b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Failed ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if ((reg5b & 0x80) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Turn off tuning, we have the DPLL set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pci_read_config_dword(dev, 0x5c, ®5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Never went stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static u32 hpt374_read_freq(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) unsigned long io_base = pci_resource_start(pdev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (PCI_FUNC(pdev->devfn) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct pci_dev *pdev_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Someone hot plugged the controller on us ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (pdev_0 == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) io_base = pci_resource_start(pdev_0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) freq = inl(io_base + 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pci_dev_put(pdev_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) freq = inl(io_base + 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * hpt37x_init_one - Initialise an HPT37X/302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * @id: Entry in match table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * Initialise an HPT37x device. There are some interesting complications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * here. Firstly the chip may report 366 and be one of several variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Secondly all the timings depend on the clock for the chip which we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * detect and look up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * This is the known chip mappings. It may be missing a couple of later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * releases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * Chip version PCI Rev Notes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * HPT366 4 (HPT366) 0 Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * HPT366 4 (HPT366) 1 Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * HPT368 4 (HPT366) 2 Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * HPT370 4 (HPT366) 3 UDMA100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * HPT370A 4 (HPT366) 4 UDMA100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * HPT372 4 (HPT366) 5 UDMA133 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * HPT372N 4 (HPT366) 6 Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * HPT372A 5 (HPT372) 1 UDMA133 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * HPT372N 5 (HPT372) 2 Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * HPT302 6 (HPT302) 1 UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * HPT302N 6 (HPT302) 2 Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * HPT371 7 (HPT371) * UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * HPT374 8 (HPT374) * UDMA133 4 channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * HPT372N 9 (HPT372N) * Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * (1) UDMA133 support depends on the bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* HPT370 - UDMA100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct ata_port_info info_hpt370 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .port_ops = &hpt370_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* HPT370A - UDMA100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static const struct ata_port_info info_hpt370a = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .port_ops = &hpt370a_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* HPT370 - UDMA66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const struct ata_port_info info_hpt370_33 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .port_ops = &hpt370_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* HPT370A - UDMA66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct ata_port_info info_hpt370a_33 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .port_ops = &hpt370a_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* HPT372 - UDMA133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const struct ata_port_info info_hpt372 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .port_ops = &hpt372_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* HPT371, 302 - UDMA133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const struct ata_port_info info_hpt302 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .port_ops = &hpt302_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* HPT374 - UDMA100, function 1 uses different cable_detect method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static const struct ata_port_info info_hpt374_fn0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .port_ops = &hpt372_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const struct ata_port_info info_hpt374_fn1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .port_ops = &hpt374_fn1_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const int MHz[4] = { 33, 40, 50, 66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) void *private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) const struct ata_port_info *ppi[] = { NULL, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u8 rev = dev->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u8 irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u8 mcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) int prefer_dpll = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) unsigned long iobase = pci_resource_start(dev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) const struct hpt_chip *chip_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int clock_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) rc = pcim_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case PCI_DEVICE_ID_TTI_HPT366:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* May be a later chip in disguise. Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Older chips are in the HPT366 driver. Ignore them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (rev < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* N series chips have their own driver. Ignore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (rev == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ppi[0] = &info_hpt370;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) chip_table = &hpt370;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) prefer_dpll = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ppi[0] = &info_hpt370a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) chip_table = &hpt370a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) prefer_dpll = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ppi[0] = &info_hpt372;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) chip_table = &hpt372;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) pr_err("Unknown HPT366 subtype, please report (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case PCI_DEVICE_ID_TTI_HPT372:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* 372N if rev >= 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (rev >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ppi[0] = &info_hpt372;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) chip_table = &hpt372a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case PCI_DEVICE_ID_TTI_HPT302:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* 302N if rev > 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (rev > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ppi[0] = &info_hpt302;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Check this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) chip_table = &hpt302;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case PCI_DEVICE_ID_TTI_HPT371:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (rev > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ppi[0] = &info_hpt302;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) chip_table = &hpt371;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * Single channel device, master is not present but the BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * (or us for non x86) must mark it absent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pci_read_config_byte(dev, 0x50, &mcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) mcr1 &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pci_write_config_byte(dev, 0x50, mcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case PCI_DEVICE_ID_TTI_HPT374:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) chip_table = &hpt374;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (!(PCI_FUNC(dev->devfn) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) *ppi = &info_hpt374_fn0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) *ppi = &info_hpt374_fn1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pr_err("PCI table is bogus, please report (%d)\n", dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Ok so this is a chip we support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pci_read_config_byte(dev, 0x5A, &irqmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) irqmask &= ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) pci_write_config_byte(dev, 0x5a, irqmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * HPT371 chips physically have only one channel, the secondary one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * but the primary channel registers do exist! Go figure...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * So, we manually disable the non-existing channel here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * (if the BIOS hasn't done this already).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u8 mcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) pci_read_config_byte(dev, 0x50, &mcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) mcr1 &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pci_write_config_byte(dev, 0x50, mcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * default to pci clock. make sure MA15/16 are set to output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * to prevent drives having problems with 40-pin cables. Needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * for some drives such as IBM-DTLA which will not enter ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * state on reset when PDIAG is a input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) pci_write_config_byte(dev, 0x5b, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * HighPoint does this for HPT372A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * NOTE: This register is only writeable via I/O space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (chip_table == &hpt372a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) outb(0x0e, iobase + 0x9c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * Some devices do not let this value be accessed via PCI space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * according to the old driver. In addition we must use the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * from FN 0 on the HPT374.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (chip_table == &hpt374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) freq = hpt374_read_freq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (freq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) freq = inl(iobase + 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if ((freq >> 12) != 0xABCDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u16 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u32 total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) pr_warn("BIOS has not set timing clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* This is the process the HPT371 BIOS is reported to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) for (i = 0; i < 128; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) pci_read_config_word(dev, 0x78, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) total += sr & 0x1FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) udelay(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) freq = total / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) freq &= 0x1FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * Turn the frequency check into a band and then find a timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * table to match it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) clock_slot = hpt37x_clock_slot(freq, chip_table->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * We need to try PLL mode instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * For non UDMA133 capable devices we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * use a 50MHz DPLL by choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned int f_low, f_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int dpll, adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* Compute DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) f_low = (MHz[clock_slot] * 48) / MHz[dpll];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) f_high = f_low + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (clock_slot > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) f_high += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* Select the DPLL clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) pci_write_config_byte(dev, 0x5b, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) pci_write_config_dword(dev, 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) (f_high << 16) | f_low | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) for (adjust = 0; adjust < 8; adjust++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (hpt37x_calibrate_dpll(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * See if it'll settle at a fractionally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * different clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (adjust & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) f_low -= adjust >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) f_high += adjust >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) pci_write_config_dword(dev, 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) (f_high << 16) | f_low | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (adjust == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pr_err("DPLL did not stabilize!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (dpll == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) private_data = (void *)hpt37x_timings_66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) private_data = (void *)hpt37x_timings_50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pr_info("bus clock %dMHz, using %dMHz DPLL\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) MHz[clock_slot], MHz[dpll]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) private_data = (void *)chip_table->clocks[clock_slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * Perform a final fixup. Note that we will have used the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * DPLL on the HPT372 which means we don't have to worry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * about lack of UDMA133 support on lower clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (clock_slot < 2 && ppi[0] == &info_hpt370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ppi[0] = &info_hpt370_33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (clock_slot < 2 && ppi[0] == &info_hpt370a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ppi[0] = &info_hpt370a_33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) pr_info("%s using %dMHz bus clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) chip_table->name, MHz[clock_slot]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Now kick off ATA set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const struct pci_device_id hpt37x[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static struct pci_driver hpt37x_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .id_table = hpt37x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .probe = hpt37x_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .remove = ata_pci_remove_one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) module_pci_driver(hpt37x_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) MODULE_DEVICE_TABLE(pci, hpt37x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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