Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This driver is heavily based upon:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Portions Copyright (C) 2003		Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *	Look into engine reset on timeout errors. Should not be required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DRV_NAME	"pata_hpt366"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DRV_VERSION	"0.6.11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct hpt_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u8	xfer_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32	timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* key for bus clock timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *        cycles = value + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *        cycles = value + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *        register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *        register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *        register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * 28     UDMA enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * 29     DMA  enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * 30     PIO_MST enable. If set, the chip is in bus master mode during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *        PIO xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * 31     FIFO enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static const struct hpt_clock hpt366_40[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{	XFER_UDMA_4,	0x900fd943	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{	XFER_UDMA_3,	0x900ad943	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{	XFER_UDMA_2,	0x900bd943	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{	XFER_UDMA_1,	0x9008d943	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{	XFER_UDMA_0,	0x9008d943	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{	XFER_MW_DMA_2,	0xa008d943	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{	XFER_MW_DMA_1,	0xa010d955	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{	XFER_MW_DMA_0,	0xa010d9fc	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{	XFER_PIO_4,	0xc008d963	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{	XFER_PIO_3,	0xc010d974	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{	XFER_PIO_2,	0xc010d997	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{	XFER_PIO_1,	0xc010d9c7	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{	XFER_PIO_0,	0xc018d9d9	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{	0,		0x0120d9d9	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static const struct hpt_clock hpt366_33[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{	XFER_UDMA_4,	0x90c9a731	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{	XFER_UDMA_3,	0x90cfa731	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{	XFER_UDMA_2,	0x90caa731	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{	XFER_UDMA_1,	0x90cba731	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{	XFER_UDMA_0,	0x90c8a731	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{	XFER_MW_DMA_2,	0xa0c8a731	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{	XFER_MW_DMA_0,	0xa0c8a797	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{	XFER_PIO_4,	0xc0c8a731	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{	XFER_PIO_3,	0xc0c8a742	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{	XFER_PIO_2,	0xc0d0a753	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{	0,		0x0120a7a7	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static const struct hpt_clock hpt366_25[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{	XFER_UDMA_4,	0x90c98521	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{	XFER_UDMA_3,	0x90cf8521	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{	XFER_UDMA_2,	0x90cf8521	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{	XFER_UDMA_1,	0x90cb8521	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{	XFER_UDMA_0,	0x90cb8521	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{	XFER_MW_DMA_2,	0xa0ca8521	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{	XFER_MW_DMA_1,	0xa0ca8532	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{	XFER_MW_DMA_0,	0xa0ca8575	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{	XFER_PIO_4,	0xc0ca8521	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{	XFER_PIO_3,	0xc0ca8532	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{	XFER_PIO_2,	0xc0ca8542	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{	XFER_PIO_1,	0xc0d08572	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{	XFER_PIO_0,	0xc0d08585	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{	0,		0x01208585	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  *	hpt36x_find_mode	-	find the hpt36x timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *	@ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  *	@speed: transfer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *	Return the 32bit register programming information for this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *	that matches the speed provided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct hpt_clock *clocks = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	while (clocks->xfer_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		if (clocks->xfer_mode == speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			return clocks->timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		clocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return 0xffffffffU;	/* silence compiler warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const char * const bad_ata33[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	"Maxtor 90845U3", "Maxtor 90650U2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	"Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	"Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	"Maxtor 90510D4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	"Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	"Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const char * const bad_ata66_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	"IBM-DTLA-307075",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	"IBM-DTLA-307060",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	"IBM-DTLA-307045",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	"IBM-DTLA-307030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	"IBM-DTLA-307020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	"IBM-DTLA-307015",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	"IBM-DTLA-305040",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	"IBM-DTLA-305030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	"IBM-DTLA-305020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	"IC35L010AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	"IC35L020AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	"IC35L030AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	"IC35L040AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	"IC35L060AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	"WDC AC310200R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const char * const bad_ata66_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	"WDC AC310200R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			       const char * const list[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	i = match_string(list, -1, model_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		pr_warn("%s is not supported for %s\n", modestr, list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  *	hpt366_filter	-	mode selection filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  *	@adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *	Block UDMA on devices that cause trouble with this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (adev->class == ATA_DEV_ATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			mask &= ~ATA_MASK_UDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			mask &= ~(0xF8 << ATA_SHIFT_UDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			mask &= ~(0xF0 << ATA_SHIFT_UDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	} else if (adev->class == ATA_DEV_ATAPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int hpt36x_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	u8 ata66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * Each channel of pata_hpt366 occupies separate PCI function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * as the primary channel and bit1 indicates the cable type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	pci_read_config_byte(pdev, 0x5A, &ata66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ata66 & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			    u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	u32 addr = 0x40 + 4 * adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u32 mask, reg, t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* determine timing mask and find matching clock entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (mode < XFER_MW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		mask = 0xc1f8ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	else if (mode < XFER_UDMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		mask = 0x303800ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		mask = 0x30070000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	t = hpt36x_find_mode(ap, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 * Combine new mode bits with old config bits and disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 * problems handling I/O errors later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	pci_read_config_dword(pdev, addr, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	pci_write_config_dword(pdev, addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  *	hpt366_set_piomode		-	PIO setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  *	@adev: device on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  *	Perform PIO mode setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	hpt366_set_mode(ap, adev, adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *	hpt366_set_dmamode		-	DMA timing setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  *	@adev: Device being configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  *	Set up the channel for MWDMA or UDMA modes. Much the same as with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  *	PIO, load the mode number and then set MWDMA or UDMA flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	hpt366_set_mode(ap, adev, adev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct scsi_host_template hpt36x_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  *	Configuration for HPT366/68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct ata_port_operations hpt366_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.inherits	= &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.cable_detect	= hpt36x_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.mode_filter	= hpt366_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.set_piomode	= hpt366_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.set_dmamode	= hpt366_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  *	hpt36x_init_chipset	-	common chip setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  *	@dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  *	Perform the chip setup work that must be done at both init and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  *	resume time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void hpt36x_init_chipset(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	u8 drive_fast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	pci_read_config_byte(dev, 0x51, &drive_fast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (drive_fast & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  *	hpt36x_init_one		-	Initialise an HPT366/368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  *	@dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  *	@id: Entry in match table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)  *	Initialise an HPT36x device. There are some interesting complications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)  *	here. Firstly the chip may report 366 and be one of several variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)  *	Secondly all the timings depend on the clock for the chip which we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)  *	detect and look up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)  *	This is the known chip mappings. It may be missing a couple of later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)  *	releases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)  *	Chip version		PCI		Rev	Notes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)  *	HPT366			4 (HPT366)	0	UDMA66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  *	HPT366			4 (HPT366)	1	UDMA66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  *	HPT368			4 (HPT366)	2	UDMA66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  *	HPT37x/30x		4 (HPT366)	3+	Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	static const struct ata_port_info info_hpt366 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.port_ops = &hpt366_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	const void *hpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	u32 reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	rc = pcim_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/* May be a later chip in disguise. Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	/* Newer chips are not in the HPT36x driver. Ignore them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (dev->revision > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	hpt36x_init_chipset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	pci_read_config_dword(dev, 0x40,  &reg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	/* PCI clocking determines the ATA timing values to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	/* info_hpt366 is safe against re-entry so we can scribble on it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	switch ((reg1 & 0xf00) >> 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		hpriv = &hpt366_40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		hpriv = &hpt366_25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		hpriv = &hpt366_33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	/* Now kick off ATA set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int hpt36x_reinit_one(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	struct ata_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	rc = ata_pci_device_do_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	hpt36x_init_chipset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const struct pci_device_id hpt36x[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct pci_driver hpt36x_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.id_table	= hpt36x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.probe		= hpt36x_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.remove		= ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.suspend	= ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.resume		= hpt36x_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) module_pci_driver(hpt36x_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MODULE_DEVICE_TABLE(pci, hpt36x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MODULE_VERSION(DRV_VERSION);