^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Faraday Technology FTIDE010 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Includes portions of the SL2312/SL3516/Gemini PATA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003 StorLine, Inc <jason@storlink.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2010 Frederic Pecourt <opengemini@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2011 Tobias Waldvogel <tobias.waldvogel@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "sata_gemini.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRV_NAME "pata_ftide010"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * struct ftide010 - state container for the Faraday FTIDE010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @dev: pointer back to the device representing this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @base: remapped I/O space address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @pclk: peripheral clock for the IDE block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @host: pointer to the ATA host for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @master_cbl: master cable type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @slave_cbl: slave cable type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @sg: Gemini SATA bridge pointer, if running on the Gemini
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @master_to_sata0: Gemini SATA bridge: the ATA master is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * to the SATA0 bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @slave_to_sata0: Gemini SATA bridge: the ATA slave is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * to the SATA0 bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @master_to_sata1: Gemini SATA bridge: the ATA master is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * to the SATA1 bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @slave_to_sata1: Gemini SATA bridge: the ATA slave is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * to the SATA1 bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct ftide010 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int master_cbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int slave_cbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Gemini-specific properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct sata_gemini *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool master_to_sata0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bool slave_to_sata0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bool master_to_sata1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool slave_to_sata1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FTIDE010_DMA_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FTIDE010_DMA_STATUS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FTIDE010_IDE_BMDTPR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FTIDE010_IDE_DEVICE_ID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FTIDE010_PIO_TIMING 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FTIDE010_MWDMA_TIMING 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FTIDE010_UDMA_TIMING0 0x12 /* Master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FTIDE010_UDMA_TIMING1 0x13 /* Slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FTIDE010_CLK_MOD 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* These registers are mapped directly to the IDE registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FTIDE010_CMD_DATA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FTIDE010_ERROR_FEATURES 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FTIDE010_NSECT 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FTIDE010_LBAL 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FTIDE010_LBAM 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FTIDE010_LBAH 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FTIDE010_DEVICE 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FTIDE010_STATUS_COMMAND 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FTIDE010_ALTSTAT_CTRL 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Set this bit for UDMA mode 5 and 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FTIDE010_UDMA_TIMING_MODE_56 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 0 = 50 MHz, 1 = 66 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FTIDE010_CLK_MOD_DEV0_CLK_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FTIDE010_CLK_MOD_DEV1_CLK_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Enable UDMA on a device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FTIDE010_CLK_MOD_DEV0_UDMA_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FTIDE010_CLK_MOD_DEV1_UDMA_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct scsi_host_template pata_ftide010_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Bus timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * The unit of the below required timings is two clock periods of the ATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * reference clock which is 30 nanoseconds per unit at 66MHz and 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * PIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * pio_active_time: array of 5 elements for T2 timing for Mode 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 1, 2, 3 and 4. Range 0..15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * pio_recovery_time: array of 5 elements for T2l timing for Mode 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 1, 2, 3 and 4. Range 0..15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * mdma_50_active_time: array of 4 elements for Td timing for multi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * mdma_50_recovery_time: array of 4 elements for Tk timing for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * mdma_66_active_time: array of 4 elements for Td timing for multi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * mdma_66_recovery_time: array of 4 elements for Tk timing for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * udma_50_setup_time: array of 4 elements for Tvds timing for ultra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * udma_50_hold_time: array of 4 elements for Tdvh timing for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * udma_66_setup_time: array of 4 elements for Tvds timing for multi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * udma_66_hold_time: array of 4 elements for Tdvh timing for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * multi word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const u8 pio_active_time[5] = {10, 10, 10, 3, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const u8 pio_recovery_time[5] = {10, 3, 1, 3, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const u8 mwdma_50_active_time[3] = {6, 2, 2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const u8 mwdma_50_recovery_time[3] = {6, 2, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const u8 mwdma_66_active_time[3] = {8, 3, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const u8 mwdma_66_recovery_time[3] = {8, 2, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const u8 udma_50_setup_time[6] = {3, 3, 2, 2, 1, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const u8 udma_50_hold_time[6] = {3, 1, 1, 1, 1, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const u8 udma_66_setup_time[7] = {4, 4, 3, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const u8 udma_66_hold_time[7] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * We set 66 MHz for all MWDMA modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const bool set_mdma_66_mhz[] = { true, true, true, true };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * We set 66 MHz for UDMA modes 3, 4 and 6 and no others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const bool set_udma_66_mhz[] = { false, false, false, true, true, false, true };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void ftide010_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct ftide010 *ftide = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 speed = adev->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 devno = adev->devno & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 udma_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 f66m_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 clkreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 timreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Target device 0 (master) or 1 (slave) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!devno) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) udma_en_mask = FTIDE010_CLK_MOD_DEV0_UDMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) f66m_en_mask = FTIDE010_CLK_MOD_DEV0_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) udma_en_mask = FTIDE010_CLK_MOD_DEV1_UDMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) f66m_en_mask = FTIDE010_CLK_MOD_DEV1_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clkreg = readb(ftide->base + FTIDE010_CLK_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clkreg &= ~udma_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clkreg &= ~f66m_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (speed & XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) i = speed & ~XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_dbg(ftide->dev, "set UDMA mode %02x, index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) speed, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clkreg |= udma_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (set_udma_66_mhz[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) clkreg |= f66m_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) timreg = udma_66_setup_time[i] << 4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) udma_66_hold_time[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) timreg = udma_50_setup_time[i] << 4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) udma_50_hold_time[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* A special bit needs to be set for modes 5 and 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (i >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) timreg |= FTIDE010_UDMA_TIMING_MODE_56;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_dbg(ftide->dev, "UDMA write clkreg = %02x, timreg = %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clkreg, timreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) writeb(clkreg, ftide->base + FTIDE010_CLK_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writeb(timreg, ftide->base + FTIDE010_UDMA_TIMING0 + devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) i = speed & ~XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_dbg(ftide->dev, "set MWDMA mode %02x, index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) speed, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (set_mdma_66_mhz[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clkreg |= f66m_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) timreg = mwdma_66_active_time[i] << 4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mwdma_66_recovery_time[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) timreg = mwdma_50_active_time[i] << 4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mwdma_50_recovery_time[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_dbg(ftide->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "MWDMA write clkreg = %02x, timreg = %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clkreg, timreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* This will affect all devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) writeb(clkreg, ftide->base + FTIDE010_CLK_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) writeb(timreg, ftide->base + FTIDE010_MWDMA_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Store the current device (master or slave) in ap->private_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * so that .qc_issue() can detect if this changes and reprogram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * the DMA settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ap->private_data = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void ftide010_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct ftide010 *ftide = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_dbg(ftide->dev, "set PIO mode %02x, index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) adev->pio_mode, pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writeb(pio_active_time[pio] << 4 | pio_recovery_time[pio],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ftide->base + FTIDE010_PIO_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * We implement our own qc_issue() callback since we may need to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * the timings differently for master and slave transfers: the CLK_MOD_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * and MWDMA_TIMING_REG is shared between master and slave, so reprogramming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * this may be necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static unsigned int ftide010_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * If the device changed, i.e. slave->master, master->slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * then set up the DMA mode again so we are sure the timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * are correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (adev != ap->private_data && ata_dma_enabled(adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ftide010_set_dmamode(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ata_bmdma_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct ata_port_operations pata_ftide010_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .set_dmamode = ftide010_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .set_piomode = ftide010_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .qc_issue = ftide010_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct ata_port_info ftide010_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .port_ops = &pata_ftide010_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #if IS_ENABLED(CONFIG_SATA_GEMINI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int pata_ftide010_gemini_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct ftide010 *ftide = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct device *dev = ftide->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct sata_gemini *sg = ftide->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int bridges = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = ata_bmdma_port_start(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (ftide->master_to_sata0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_info(dev, "SATA0 (master) start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = gemini_sata_start_bridge(sg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bridges++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ftide->master_to_sata1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_info(dev, "SATA1 (master) start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = gemini_sata_start_bridge(sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) bridges++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Avoid double-starting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ftide->slave_to_sata0 && !ftide->master_to_sata0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_info(dev, "SATA0 (slave) start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = gemini_sata_start_bridge(sg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bridges++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Avoid double-starting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ftide->slave_to_sata1 && !ftide->master_to_sata1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_info(dev, "SATA1 (slave) start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = gemini_sata_start_bridge(sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bridges++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_info(dev, "brought %d bridges online\n", bridges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return (bridges > 0) ? 0 : -EINVAL; // -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void pata_ftide010_gemini_port_stop(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct ftide010 *ftide = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct device *dev = ftide->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct sata_gemini *sg = ftide->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ftide->master_to_sata0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_info(dev, "SATA0 (master) stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) gemini_sata_stop_bridge(sg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ftide->master_to_sata1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_info(dev, "SATA1 (master) stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) gemini_sata_stop_bridge(sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Avoid double-stopping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (ftide->slave_to_sata0 && !ftide->master_to_sata0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_info(dev, "SATA0 (slave) stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) gemini_sata_stop_bridge(sg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Avoid double-stopping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ftide->slave_to_sata1 && !ftide->master_to_sata1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_info(dev, "SATA1 (slave) stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) gemini_sata_stop_bridge(sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int pata_ftide010_gemini_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct ftide010 *ftide = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Return the master cable, I have no clue how to return a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * cable for the slave than for the master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ftide->master_cbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int pata_ftide010_gemini_init(struct ftide010 *ftide,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct ata_port_info *pi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) bool is_ata1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct device *dev = ftide->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct sata_gemini *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) enum gemini_muxmode muxmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Look up SATA bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) sg = gemini_sata_bridge_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (IS_ERR(sg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return PTR_ERR(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ftide->sg = sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) muxmode = gemini_sata_get_muxmode(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Special ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pata_ftide010_port_ops.port_start =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pata_ftide010_gemini_port_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pata_ftide010_port_ops.port_stop =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pata_ftide010_gemini_port_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pata_ftide010_port_ops.cable_detect =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pata_ftide010_gemini_cable_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Flag port as SATA-capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (gemini_sata_bridge_enabled(sg, is_ata1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pi->flags |= ATA_FLAG_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* This device has broken DMA, only PIO works */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (of_machine_is_compatible("itian,sq201")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pi->mwdma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pi->udma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * We assume that a simple 40-wire cable is used in the PATA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * if you're adding a system using the PATA interface, make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * the right cable is set up here, it might be necessary to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * special hardware detection or encode the cable type in the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * tree with special properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!is_ata1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) switch (muxmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case GEMINI_MUXMODE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ftide->master_cbl = ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ftide->slave_cbl = ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ftide->master_to_sata0 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case GEMINI_MUXMODE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ftide->master_cbl = ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ftide->slave_cbl = ATA_CBL_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ftide->master_to_sata0 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case GEMINI_MUXMODE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ftide->master_cbl = ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ftide->slave_cbl = ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case GEMINI_MUXMODE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ftide->master_cbl = ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ftide->slave_cbl = ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ftide->master_to_sata0 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ftide->slave_to_sata1 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) switch (muxmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case GEMINI_MUXMODE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ftide->master_cbl = ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ftide->slave_cbl = ATA_CBL_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ftide->master_to_sata1 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case GEMINI_MUXMODE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ftide->master_cbl = ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ftide->slave_cbl = ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ftide->master_to_sata1 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case GEMINI_MUXMODE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ftide->master_cbl = ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ftide->slave_cbl = ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ftide->slave_to_sata0 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ftide->master_to_sata1 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case GEMINI_MUXMODE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ftide->master_cbl = ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ftide->slave_cbl = ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_info(dev, "set up Gemini PATA%d\n", is_ata1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int pata_ftide010_gemini_init(struct ftide010 *ftide,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct ata_port_info *pi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) bool is_ata1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int pata_ftide010_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct ata_port_info pi = ftide010_port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) const struct ata_port_info *ppi[] = { &pi, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct ftide010 *ftide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ftide = devm_kzalloc(dev, sizeof(*ftide), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!ftide)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ftide->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ftide->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (IS_ERR(ftide->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return PTR_ERR(ftide->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ftide->pclk = devm_clk_get(dev, "PCLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!IS_ERR(ftide->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = clk_prepare_enable(ftide->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(dev, "failed to enable PCLK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Some special Cortina Gemini init, if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (of_device_is_compatible(np, "cortina,gemini-pata")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * We need to know which instance is probing (the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Gemini has two instances of FTIDE010) and we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * this simply by looking at the physical base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * address, which is 0x63400000 for ATA1, else we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * are ATA0. This will also set up the cable types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = pata_ftide010_gemini_init(ftide,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &pi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) (res->start == 0x63400000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto err_dis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Else assume we are connected using PATA40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ftide->master_cbl = ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ftide->slave_cbl = ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ftide->host = ata_host_alloc_pinfo(dev, ppi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!ftide->host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) goto err_dis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ftide->host->private_data = ftide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) for (i = 0; i < ftide->host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct ata_port *ap = ftide->host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ioaddr->bmdma_addr = ftide->base + FTIDE010_DMA_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ioaddr->cmd_addr = ftide->base + FTIDE010_CMD_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ioaddr->ctl_addr = ftide->base + FTIDE010_ALTSTAT_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ioaddr->altstatus_addr = ftide->base + FTIDE010_ALTSTAT_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ata_sff_std_ports(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_info(dev, "device ID %08x, irq %d, reg %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) readl(ftide->base + FTIDE010_IDE_DEVICE_ID), irq, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = ata_host_activate(ftide->host, irq, ata_bmdma_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 0, &pata_ftide010_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto err_dis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) err_dis_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!IS_ERR(ftide->pclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) clk_disable_unprepare(ftide->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int pata_ftide010_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct ata_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct ftide010 *ftide = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ata_host_detach(ftide->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!IS_ERR(ftide->pclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) clk_disable_unprepare(ftide->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct of_device_id pata_ftide010_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .compatible = "faraday,ftide010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static struct platform_driver pata_ftide010_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .of_match_table = of_match_ptr(pata_ftide010_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .probe = pata_ftide010_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .remove = pata_ftide010_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) module_platform_driver(pata_ftide010_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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