^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * EP93XX PATA controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012, Metasoft s.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Rafal Prylowski <prylowski@metasoft.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on pata_scc.c, pata_icside.c and on earlier version of EP93XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * PATA driver by Lennert Buytenhek and Alessandro Zummo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Read/Write timings, resource management and other improvements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * from driver by Joao Ramos and Bartlomiej Zolnierkiewicz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * DMA engine support based on spi-ep93xx.c by Mika Westerberg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Original copyrights:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Support for Cirrus Logic's EP93xx (EP9312, EP9315) CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * PATA host controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright (c) 2009, Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Heavily based on the ep93xx-ide.c driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Copyright (c) 2009, Joao Ramos <joao.ramos@inov.pt>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * INESC Inovacao (INOV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * EP93XX PATA controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * An ATA driver for the Cirrus Logic EP93xx PATA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Based on an earlier version by Alessandro Zummo, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Copyright (C) 2006 Tower Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/platform_data/dma-ep93xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/soc/cirrus/ep93xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DRV_NAME "ep93xx-ide"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRV_VERSION "1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* IDE Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) IDECTRL = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) IDECTRL_CS0N = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) IDECTRL_CS1N = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) IDECTRL_DIORN = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) IDECTRL_DIOWN = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) IDECTRL_INTRQ = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) IDECTRL_IORDY = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * the device IDE register to be accessed is selected through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * IDECTRL register's specific bitfields 'DA', 'CS1N' and 'CS0N':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * b4 b3 b2 b1 b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * A2 A1 A0 CS1N CS0N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * the values filled in this structure allows the value to be directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * ORed to the IDECTRL register, hence giving directly the A[2:0] and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * CS1N/CS0N values for each IDE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * The values correspond to the transformation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * ((real IDE address) << 2) | CS1N value << 1 | CS0N value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) IDECTRL_ADDR_CMD = 0 + 2, /* CS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) IDECTRL_ADDR_DATA = (ATA_REG_DATA << 2) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) IDECTRL_ADDR_ERROR = (ATA_REG_ERR << 2) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) IDECTRL_ADDR_FEATURE = (ATA_REG_FEATURE << 2) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) IDECTRL_ADDR_NSECT = (ATA_REG_NSECT << 2) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) IDECTRL_ADDR_LBAL = (ATA_REG_LBAL << 2) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) IDECTRL_ADDR_LBAM = (ATA_REG_LBAM << 2) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) IDECTRL_ADDR_LBAH = (ATA_REG_LBAH << 2) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) IDECTRL_ADDR_DEVICE = (ATA_REG_DEVICE << 2) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) IDECTRL_ADDR_STATUS = (ATA_REG_STATUS << 2) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) IDECTRL_ADDR_COMMAND = (ATA_REG_CMD << 2) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) IDECTRL_ADDR_ALTSTATUS = (0x06 << 2) + 1, /* CS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) IDECTRL_ADDR_CTL = (0x06 << 2) + 1, /* CS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* IDE Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) IDECFG = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) IDECFG_IDEEN = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) IDECFG_PIO = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) IDECFG_MDMA = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) IDECFG_UDMA = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) IDECFG_MODE_SHIFT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) IDECFG_MODE_MASK = (0xf << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) IDECFG_WST_SHIFT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) IDECFG_WST_MASK = (0x3 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* MDMA Operation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) IDEMDMAOP = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* UDMA Operation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) IDEUDMAOP = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) IDEUDMAOP_UEN = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) IDEUDMAOP_RWOP = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* PIO/MDMA/UDMA Data Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) IDEDATAOUT = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) IDEDATAIN = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) IDEMDMADATAOUT = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) IDEMDMADATAIN = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) IDEUDMADATAOUT = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) IDEUDMADATAIN = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* UDMA Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) IDEUDMASTS = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) IDEUDMASTS_DMAIDE = (1 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) IDEUDMASTS_INTIDE = (1 << 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) IDEUDMASTS_SBUSY = (1 << 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) IDEUDMASTS_NDO = (1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) IDEUDMASTS_NDI = (1 << 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) IDEUDMASTS_N4X = (1 << 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* UDMA Debug Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) IDEUDMADEBUG = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct ep93xx_pata_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void __iomem *ide_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bool iordy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long udma_in_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long udma_out_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct dma_chan *dma_rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct ep93xx_dma_data dma_rx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct dma_chan *dma_tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct ep93xx_dma_data dma_tx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void ep93xx_pata_clear_regs(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel(IDECTRL_CS0N | IDECTRL_CS1N | IDECTRL_DIORN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) IDECTRL_DIOWN, base + IDECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(0, base + IDECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(0, base + IDEMDMAOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writel(0, base + IDEUDMAOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) writel(0, base + IDEDATAOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writel(0, base + IDEDATAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) writel(0, base + IDEMDMADATAOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(0, base + IDEMDMADATAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel(0, base + IDEUDMADATAOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writel(0, base + IDEUDMADATAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel(0, base + IDEUDMADEBUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static bool ep93xx_pata_check_iordy(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return !!(readl(base + IDECTRL) & IDECTRL_IORDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * According to EP93xx User's Guide, WST field of IDECFG specifies number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * of HCLK cycles to hold the data bus after a PIO write operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * It should be programmed to guarantee following delays:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * PIO Mode [ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * 0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * 1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * 2 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * 3 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * 4 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Maximum possible value for HCLK is 100MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int ep93xx_pata_get_wst(int pio_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (pio_mode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) val = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) else if (pio_mode < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return val << IDECFG_WST_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void ep93xx_pata_enable_pio(void __iomem *base, int pio_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writel(IDECFG_IDEEN | IDECFG_PIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ep93xx_pata_get_wst(pio_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) (pio_mode << IDECFG_MODE_SHIFT), base + IDECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Based on delay loop found in mach-pxa/mp900.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Single iteration should take 5 cpu cycles. This is 25ns assuming the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * fastest ep93xx cpu speed (200MHz) and is better optimized for PIO4 timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * than eg. 20ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void ep93xx_pata_delay(unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __asm__ volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "0:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "mov r0, r0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "subs %0, %1, #1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "bge 0b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) : "=r" (count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) : "0" (count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static unsigned long ep93xx_pata_wait_for_iordy(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned long t2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * According to ATA specification, IORDY pin can be first sampled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * tA = 35ns after activation of DIOR-/DIOW-. Maximum IORDY pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * width is tB = 1250ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * We are already t2 delay loop iterations after activation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * DIOR-/DIOW-, so we set timeout to (1250 + 35) / 25 - t2 additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * delay loop iterations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned long start = (1250 + 35) / 25 - t2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long counter = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) while (!ep93xx_pata_check_iordy(base) && counter--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ep93xx_pata_delay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return start - counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* common part at start of ep93xx_pata_read/write() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void ep93xx_pata_rw_begin(void __iomem *base, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long t1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ep93xx_pata_delay(t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* common part at end of ep93xx_pata_read/write() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void ep93xx_pata_rw_end(void __iomem *base, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bool iordy, unsigned long t0, unsigned long t2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned long t2i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ep93xx_pata_delay(t2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* lengthen t2 if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (iordy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) t2 += ep93xx_pata_wait_for_iordy(base, t2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (t0 > t2 && t0 - t2 > t2i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ep93xx_pata_delay(t0 - t2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ep93xx_pata_delay(t2i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static u16 ep93xx_pata_read(struct ep93xx_pata_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bool reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) void __iomem *base = drv_data->ide_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const struct ata_timing *t = &drv_data->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned long t0 = reg ? t->cyc8b : t->cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned long t2 = reg ? t->act8b : t->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long t2i = reg ? t->rec8b : t->recover;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ep93xx_pata_rw_begin(base, addr, t->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writel(IDECTRL_DIOWN | addr, base + IDECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * The IDEDATAIN register is loaded from the DD pins at the positive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * edge of the DIORN signal. (EP93xx UG p27-14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return readl(base + IDEDATAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* IDE register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static u16 ep93xx_pata_read_reg(struct ep93xx_pata_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ep93xx_pata_read(drv_data, addr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* PIO data read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static u16 ep93xx_pata_read_data(struct ep93xx_pata_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ep93xx_pata_read(drv_data, addr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void ep93xx_pata_write(struct ep93xx_pata_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u16 value, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bool reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void __iomem *base = drv_data->ide_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) const struct ata_timing *t = &drv_data->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long t0 = reg ? t->cyc8b : t->cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long t2 = reg ? t->act8b : t->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long t2i = reg ? t->rec8b : t->recover;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ep93xx_pata_rw_begin(base, addr, t->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Value from IDEDATAOUT register is driven onto the DD pins when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * DIOWN is low. (EP93xx UG p27-13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(value, base + IDEDATAOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) writel(IDECTRL_DIORN | addr, base + IDECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* IDE register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void ep93xx_pata_write_reg(struct ep93xx_pata_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u16 value, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ep93xx_pata_write(drv_data, value, addr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* PIO data write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void ep93xx_pata_write_data(struct ep93xx_pata_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u16 value, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ep93xx_pata_write(drv_data, value, addr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void ep93xx_pata_set_piomode(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Calculate timings for the delay loop, assuming ep93xx cpu speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * is 200MHz (maximum possible for ep93xx). If actual cpu speed is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * slower, we will wait a bit longer in each delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Additional division of cpu speed by 5, because single iteration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * of our delay loop takes 5 cpu cycles (25ns).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned long T = 1000000 / (200 / 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ata_timing_compute(adev, adev->pio_mode, &drv_data->t, T, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (pair && pair->pio_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ata_timing_compute(pair, pair->pio_mode, &t, T, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ata_timing_merge(&t, &drv_data->t, &drv_data->t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ATA_TIMING_SETUP | ATA_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) drv_data->iordy = ata_pio_need_iordy(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ep93xx_pata_enable_pio(drv_data->ide_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) adev->pio_mode - XFER_PIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Note: original code is ata_sff_check_status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static u8 ep93xx_pata_check_status(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static u8 ep93xx_pata_check_altstatus(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_ALTSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Note: original code is ata_sff_tf_load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void ep93xx_pata_tf_load(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (tf->ctl != ap->last_ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ap->last_ctl = tf->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ep93xx_pata_write_reg(drv_data, tf->hob_feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) IDECTRL_ADDR_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ep93xx_pata_write_reg(drv_data, tf->hob_nsect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) IDECTRL_ADDR_NSECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ep93xx_pata_write_reg(drv_data, tf->hob_lbal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) IDECTRL_ADDR_LBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ep93xx_pata_write_reg(drv_data, tf->hob_lbam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) IDECTRL_ADDR_LBAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ep93xx_pata_write_reg(drv_data, tf->hob_lbah,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) IDECTRL_ADDR_LBAH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (is_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ep93xx_pata_write_reg(drv_data, tf->feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) IDECTRL_ADDR_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ep93xx_pata_write_reg(drv_data, tf->nsect, IDECTRL_ADDR_NSECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ep93xx_pata_write_reg(drv_data, tf->lbal, IDECTRL_ADDR_LBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ep93xx_pata_write_reg(drv_data, tf->lbam, IDECTRL_ADDR_LBAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ep93xx_pata_write_reg(drv_data, tf->lbah, IDECTRL_ADDR_LBAH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (tf->flags & ATA_TFLAG_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ep93xx_pata_write_reg(drv_data, tf->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) IDECTRL_ADDR_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Note: original code is ata_sff_tf_read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void ep93xx_pata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tf->command = ep93xx_pata_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tf->feature = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tf->nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tf->lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) tf->lbam = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) tf->lbah = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) tf->device = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (tf->flags & ATA_TFLAG_LBA48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ep93xx_pata_write_reg(drv_data, tf->ctl | ATA_HOB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) IDECTRL_ADDR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) tf->hob_feature = ep93xx_pata_read_reg(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) IDECTRL_ADDR_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tf->hob_nsect = ep93xx_pata_read_reg(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) IDECTRL_ADDR_NSECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tf->hob_lbal = ep93xx_pata_read_reg(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) IDECTRL_ADDR_LBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) tf->hob_lbam = ep93xx_pata_read_reg(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) IDECTRL_ADDR_LBAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) tf->hob_lbah = ep93xx_pata_read_reg(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) IDECTRL_ADDR_LBAH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ap->last_ctl = tf->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Note: original code is ata_sff_exec_command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static void ep93xx_pata_exec_command(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ep93xx_pata_write_reg(drv_data, tf->command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) IDECTRL_ADDR_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ata_sff_pause(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Note: original code is ata_sff_dev_select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void ep93xx_pata_dev_select(struct ata_port *ap, unsigned int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u8 tmp = ATA_DEVICE_OBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (device != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tmp |= ATA_DEV1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ep93xx_pata_write_reg(drv_data, tmp, IDECTRL_ADDR_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ata_sff_pause(ap); /* needed; also flushes, for mmio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Note: original code is ata_sff_set_devctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void ep93xx_pata_set_devctl(struct ata_port *ap, u8 ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ep93xx_pata_write_reg(drv_data, ctl, IDECTRL_ADDR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Note: original code is ata_sff_data_xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static unsigned int ep93xx_pata_data_xfer(struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned int buflen, int rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct ata_port *ap = qc->dev->link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u16 *data = (u16 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned int words = buflen >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Transfer multiple of 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) while (words--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (rw == READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) *data++ = cpu_to_le16(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ep93xx_pata_read_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) drv_data, IDECTRL_ADDR_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ep93xx_pata_write_data(drv_data, le16_to_cpu(*data++),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) IDECTRL_ADDR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Transfer trailing 1 byte, if any. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (unlikely(buflen & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned char pad[2] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) buf += buflen - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (rw == READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) *pad = cpu_to_le16(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ep93xx_pata_read_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) drv_data, IDECTRL_ADDR_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) *buf = pad[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pad[0] = *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ep93xx_pata_write_data(drv_data, le16_to_cpu(*pad),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) IDECTRL_ADDR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) words++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return words << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Note: original code is ata_devchk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static bool ep93xx_pata_device_is_present(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u8 nsect, lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ap->ops->sff_dev_select(ap, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_NSECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_LBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if ((nsect == 0x55) && (lbal == 0xaa))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Note: original code is ata_sff_wait_after_reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int ep93xx_pata_wait_after_reset(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned int devmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned int dev0 = devmask & (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int dev1 = devmask & (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int rc, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ata_msleep(ap, ATA_WAIT_AFTER_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* always check readiness of the master device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) rc = ata_sff_wait_ready(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * -ENODEV means the odd clown forgot the D7 pulldown resistor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * and TF status is 0xff, bail out on it too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * if device 1 was found in ata_devchk, wait for register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * access briefly, then wait for BSY to clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (dev1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ap->ops->sff_dev_select(ap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * Wait for register access. Some ATAPI devices fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * to set nsect/lbal after reset, so don't waste too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * much time on it. We're gonna wait for !BSY anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u8 nsect, lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) nsect = ep93xx_pata_read_reg(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) IDECTRL_ADDR_NSECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) lbal = ep93xx_pata_read_reg(drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) IDECTRL_ADDR_LBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (nsect == 1 && lbal == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) msleep(50); /* give drive a breather */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) rc = ata_sff_wait_ready(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (rc != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* is all this really necessary? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ap->ops->sff_dev_select(ap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (dev1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ap->ops->sff_dev_select(ap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (dev0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ap->ops->sff_dev_select(ap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Note: original code is ata_bus_softreset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int ep93xx_pata_bus_softreset(struct ata_port *ap, unsigned int devmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) udelay(20); /* FIXME: flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ep93xx_pata_write_reg(drv_data, ap->ctl | ATA_SRST, IDECTRL_ADDR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) udelay(20); /* FIXME: flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ap->last_ctl = ap->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ep93xx_pata_wait_after_reset(&ap->link, devmask, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static void ep93xx_pata_release_dma(struct ep93xx_pata_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (drv_data->dma_rx_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dma_release_channel(drv_data->dma_rx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) drv_data->dma_rx_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (drv_data->dma_tx_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dma_release_channel(drv_data->dma_tx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) drv_data->dma_tx_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static bool ep93xx_pata_dma_filter(struct dma_chan *chan, void *filter_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (ep93xx_dma_chan_is_m2p(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) chan->private = filter_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static void ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) const struct platform_device *pdev = drv_data->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct dma_slave_config conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * Request two channels for IDE. Another possibility would be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * to request only one channel, and reprogram it's direction at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * start of new transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) drv_data->dma_rx_data.port = EP93XX_DMA_IDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) drv_data->dma_rx_data.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) drv_data->dma_rx_data.name = "ep93xx-pata-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) drv_data->dma_rx_channel = dma_request_channel(mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ep93xx_pata_dma_filter, &drv_data->dma_rx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!drv_data->dma_rx_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) drv_data->dma_tx_data.port = EP93XX_DMA_IDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) drv_data->dma_tx_data.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) drv_data->dma_tx_data.name = "ep93xx-pata-tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) drv_data->dma_tx_channel = dma_request_channel(mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ep93xx_pata_dma_filter, &drv_data->dma_tx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (!drv_data->dma_tx_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dma_release_channel(drv_data->dma_rx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Configure receive channel direction and source address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) memset(&conf, 0, sizeof(conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) conf.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) conf.src_addr = drv_data->udma_in_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (dmaengine_slave_config(drv_data->dma_rx_channel, &conf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(&pdev->dev, "failed to configure rx dma channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ep93xx_pata_release_dma(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Configure transmit channel direction and destination address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) memset(&conf, 0, sizeof(conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) conf.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) conf.dst_addr = drv_data->udma_out_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (dmaengine_slave_config(drv_data->dma_tx_channel, &conf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_err(&pdev->dev, "failed to configure tx dma channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ep93xx_pata_release_dma(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void ep93xx_pata_dma_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct dma_async_tx_descriptor *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) void __iomem *base = drv_data->ide_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 v = qc->dma_dir == DMA_TO_DEVICE ? IDEUDMAOP_RWOP : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) txd = dmaengine_prep_slave_sg(channel, qc->sg, qc->n_elem, qc->dma_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (!txd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_err(qc->ap->dev, "failed to prepare slave for sg dma\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) txd->callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) txd->callback_param = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (dmaengine_submit(txd) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_err(qc->ap->dev, "failed to submit dma transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dma_async_issue_pending(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * When enabling UDMA operation, IDEUDMAOP register needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * programmed in three step sequence:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * 1) set or clear the RWOP bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * 2) perform dummy read of the register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * 3) set the UEN bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) writel(v, base + IDEUDMAOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) readl(base + IDEUDMAOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) writel(v | IDEUDMAOP_UEN, base + IDEUDMAOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) writel(IDECFG_IDEEN | IDECFG_UDMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ((adev->xfer_mode - XFER_UDMA_0) << IDECFG_MODE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) base + IDECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static void ep93xx_pata_dma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) void __iomem *base = drv_data->ide_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* terminate all dma transfers, if not yet finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dmaengine_terminate_all(drv_data->dma_rx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dmaengine_terminate_all(drv_data->dma_tx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * To properly stop IDE-DMA, IDEUDMAOP register must to be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * and IDECTRL register must be set to default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) writel(0, base + IDEUDMAOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) writel(readl(base + IDECTRL) | IDECTRL_DIOWN | IDECTRL_DIORN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) IDECTRL_CS0N | IDECTRL_CS1N, base + IDECTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ep93xx_pata_enable_pio(drv_data->ide_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) qc->dev->pio_mode - XFER_PIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ata_sff_dma_pause(qc->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static void ep93xx_pata_dma_setup(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static u8 ep93xx_pata_dma_status(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 val = readl(drv_data->ide_base + IDEUDMASTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * UDMA Status Register bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * DMAIDE - DMA request signal from UDMA state machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * INTIDE - INT line generated by UDMA because of errors in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * state machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * SBUSY - UDMA state machine busy, not in idle state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * NDO - error for data-out not completed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * NDI - error for data-in not completed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * N4X - error for data transferred not multiplies of four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * 32-bit words.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * (EP93xx UG p27-17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (val & IDEUDMASTS_NDO || val & IDEUDMASTS_NDI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) val & IDEUDMASTS_N4X || val & IDEUDMASTS_INTIDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ATA_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* read INTRQ (INT[3]) pin input state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (readl(drv_data->ide_base + IDECTRL) & IDECTRL_INTRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ATA_DMA_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (val & IDEUDMASTS_SBUSY || val & IDEUDMASTS_DMAIDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return ATA_DMA_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Note: original code is ata_sff_softreset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int ep93xx_pata_softreset(struct ata_link *al, unsigned int *classes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct ata_port *ap = al->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) unsigned int devmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u8 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* determine if device 0/1 are present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (ep93xx_pata_device_is_present(ap, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) devmask |= (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (slave_possible && ep93xx_pata_device_is_present(ap, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) devmask |= (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* select device 0 again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ap->ops->sff_dev_select(al->ap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* issue bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) rc = ep93xx_pata_bus_softreset(ap, devmask, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* if link is ocuppied, -ENODEV too is an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (rc && (rc != -ENODEV || sata_scr_valid(al))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ata_link_err(al, "SRST failed (errno=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* determine by signature whether we have ATA or ATAPI devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) classes[0] = ata_sff_dev_classify(&al->device[0], devmask & (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (slave_possible && err != 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) classes[1] = ata_sff_dev_classify(&al->device[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) devmask & (1 << 1), &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* Note: original code is ata_sff_drain_fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static void ep93xx_pata_drain_fifo(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct ep93xx_pata_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* We only need to flush incoming data when a command was running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Drain up to 64K of data before we give up this recovery method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) && count < 65536; count += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* Can become DEBUG later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ata_port_dbg(ap, "drained %d bytes to clear DRQ.\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int ep93xx_pata_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct ep93xx_pata_data *drv_data = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * Set timings to safe values at startup (= number of ns from ATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * specification), we'll switch to properly calculated values later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) drv_data->t = *ata_timing_find_mode(XFER_PIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static struct scsi_host_template ep93xx_pata_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ATA_BASE_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* ep93xx dma implementation limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .sg_tablesize = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* ep93xx dma can't transfer 65536 bytes at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .dma_boundary = 0x7fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static struct ata_port_operations ep93xx_pata_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .qc_prep = ata_noop_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .softreset = ep93xx_pata_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .hardreset = ATA_OP_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .sff_dev_select = ep93xx_pata_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .sff_set_devctl = ep93xx_pata_set_devctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .sff_check_status = ep93xx_pata_check_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .sff_check_altstatus = ep93xx_pata_check_altstatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .sff_tf_load = ep93xx_pata_tf_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .sff_tf_read = ep93xx_pata_tf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .sff_exec_command = ep93xx_pata_exec_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .sff_data_xfer = ep93xx_pata_data_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .sff_drain_fifo = ep93xx_pata_drain_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .sff_irq_clear = ATA_OP_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .set_piomode = ep93xx_pata_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .bmdma_setup = ep93xx_pata_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .bmdma_start = ep93xx_pata_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .bmdma_stop = ep93xx_pata_dma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .bmdma_status = ep93xx_pata_dma_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .cable_detect = ata_cable_unknown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .port_start = ep93xx_pata_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int ep93xx_pata_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct ep93xx_pata_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct resource *mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) void __iomem *ide_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) err = ep93xx_ide_acquire_gpio(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) err = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) goto err_rel_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ide_base = devm_ioremap_resource(&pdev->dev, mem_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (IS_ERR(ide_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) err = PTR_ERR(ide_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) goto err_rel_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (!drv_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) goto err_rel_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) drv_data->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) drv_data->ide_base = ide_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) drv_data->udma_in_phys = mem_res->start + IDEUDMADATAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) drv_data->udma_out_phys = mem_res->start + IDEUDMADATAOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ep93xx_pata_dma_init(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* allocate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) host = ata_host_alloc(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) goto err_rel_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ep93xx_pata_clear_regs(ide_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) host->private_data = drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ap->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ap->ops = &ep93xx_pata_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ap->flags |= ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ap->pio_mask = ATA_PIO4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * Maximum UDMA modes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * EP931x rev.E0 - UDMA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * EP931x rev.E1 - UDMA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * EP931x rev.E2 - UDMA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * MWDMA support was removed from EP931x rev.E2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * so this driver supports only UDMA modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int chip_rev = ep93xx_chip_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (chip_rev == EP93XX_CHIP_REV_E1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ap->udma_mask = ATA_UDMA3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) else if (chip_rev == EP93XX_CHIP_REV_E2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ap->udma_mask = ATA_UDMA4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ap->udma_mask = ATA_UDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* defaults, pio 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ep93xx_pata_enable_pio(ide_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_info(&pdev->dev, "version " DRV_VERSION "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* activate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) err = ata_host_activate(host, irq, ata_bmdma_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) &ep93xx_pata_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (err == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) err_rel_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ep93xx_pata_release_dma(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) err_rel_gpio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ep93xx_ide_release_gpio(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static int ep93xx_pata_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct ata_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct ep93xx_pata_data *drv_data = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ata_host_detach(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ep93xx_pata_release_dma(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ep93xx_pata_clear_regs(drv_data->ide_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ep93xx_ide_release_gpio(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static struct platform_driver ep93xx_pata_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .probe = ep93xx_pata_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .remove = ep93xx_pata_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) module_platform_driver(ep93xx_pata_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) MODULE_AUTHOR("Alessandro Zummo, Lennert Buytenhek, Joao Ramos, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) "Bartlomiej Zolnierkiewicz, Rafal Prylowski");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) MODULE_DESCRIPTION("low-level driver for cirrus ep93xx IDE controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) MODULE_ALIAS("platform:pata_ep93xx");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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