^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_cypress.c - Cypress PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) 2006 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Alan Cox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based heavily on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * linux/drivers/ide/pci/cy82c693.c Version 0.40 Sep. 10, 2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DRV_NAME "pata_cypress"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRV_VERSION "0.1.5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* here are the offset definitions for the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) CY82_IDE_CMDREG = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) CY82_IDE_ADDRSETUP = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) CY82_IDE_MASTER_IOR = 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) CY82_IDE_MASTER_IOW = 0x4D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CY82_IDE_SLAVE_IOR = 0x4E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) CY82_IDE_SLAVE_IOW = 0x4F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CY82_IDE_MASTER_8BIT = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CY82_IDE_SLAVE_8BIT = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CY82_INDEX_PORT = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CY82_DATA_PORT = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CY82_INDEX_CTRLREG1 = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CY82_INDEX_CHANNEL0 = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CY82_INDEX_CHANNEL1 = 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CY82_INDEX_TIMEOUT = 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * cy82c693_set_piomode - set initial PIO mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Called to do the PIO mode setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void cy82c693_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const unsigned long T = 1000000 / 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) short time_16, time_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) printk(KERN_ERR DRV_NAME ": mome computation failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) time_16 = clamp_val(t.recover - 1, 0, 15) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (clamp_val(t.active - 1, 0, 15) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) time_8 = clamp_val(t.act8b - 1, 0, 15) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (clamp_val(t.rec8b - 1, 0, 15) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (adev->devno == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) addr &= ~0x0F; /* Mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) addr |= clamp_val(t.setup - 1, 0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pci_write_config_byte(pdev, CY82_IDE_MASTER_IOR, time_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pci_write_config_byte(pdev, CY82_IDE_MASTER_IOW, time_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pci_write_config_byte(pdev, CY82_IDE_MASTER_8BIT, time_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pci_read_config_dword(pdev, CY82_IDE_ADDRSETUP, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) addr &= ~0xF0; /* Mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) addr |= (clamp_val(t.setup - 1, 0, 15) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pci_write_config_dword(pdev, CY82_IDE_ADDRSETUP, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pci_write_config_byte(pdev, CY82_IDE_SLAVE_IOR, time_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pci_write_config_byte(pdev, CY82_IDE_SLAVE_IOW, time_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pci_write_config_byte(pdev, CY82_IDE_SLAVE_8BIT, time_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * cy82c693_set_dmamode - set initial DMA mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Called to do the DMA mode setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void cy82c693_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int reg = CY82_INDEX_CHANNEL0 + ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Be afraid, be very afraid. Magic registers in low I/O space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) outb(reg, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) outb(adev->dma_mode - XFER_MW_DMA_0, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* 0x50 gives the best behaviour on the Alpha's using this chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) outb(CY82_INDEX_TIMEOUT, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) outb(0x50, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct scsi_host_template cy82c693_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct ata_port_operations cy82c693_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .set_piomode = cy82c693_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .set_dmamode = cy82c693_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int cy82c693_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .port_ops = &cy82c693_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Devfn 1 is the ATA primary. The secondary is magic and on devfn2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) For the moment we don't handle the secondary. FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (PCI_FUNC(pdev->devfn) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return ata_pci_bmdma_init_one(pdev, ppi, &cy82c693_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct pci_device_id cy82c693[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct pci_driver cy82c693_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .id_table = cy82c693,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .probe = cy82c693_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .resume = ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) module_pci_driver(cy82c693_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MODULE_DESCRIPTION("low-level driver for the CY82C693 PATA controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_DEVICE_TABLE(pci, cy82c693);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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