Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * pata_cs5536.c	- CS5536 PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *			  (C) 2007 Martin K. Petersen <mkp@mkp.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *			  (C) 2011 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	Available from AMD web site.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * The IDE timing registers for the CS5536 live in the Geode Machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Specific Register file and not PCI config space.  Most BIOSes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * virtualize the PCI registers so the chip looks like a standard IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * controller.	Unfortunately not all implementations get this right.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * In particular some have problems with unaligned accesses to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * virtualized PCI registers.  This driver always does full dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * writes to work around the issue.  Also, in case of a bad BIOS this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * driver can be loaded with the "msr=1" parameter which forces using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * the Machine Specific Registers to configure the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int use_msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) module_param_named(msr, use_msr, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #undef rdmsr	/* avoid accidental MSR usage on, e.g. x86-64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #undef wrmsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define rdmsr(x, y, z) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define wrmsr(x, y, z) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define use_msr 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DRV_NAME	"pata_cs5536"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DRV_VERSION	"0.0.8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	MSR_IDE_CFG		= 0x51300010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	PCI_IDE_CFG		= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	CFG			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	DTC			= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	CAST			= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	ETC			= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	IDE_CFG_CHANEN		= (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	IDE_CFG_CABLE		= (1 << 17) | (1 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	IDE_D0_SHIFT		= 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	IDE_D1_SHIFT		= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	IDE_DRV_MASK		= 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	IDE_CAST_D0_SHIFT	= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	IDE_CAST_D1_SHIFT	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	IDE_CAST_DRV_MASK	= 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	IDE_CAST_CMD_MASK	= 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	IDE_CAST_CMD_SHIFT	= 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	IDE_ETC_UDMA_MASK	= 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* Some Bachmann OT200 devices have a non working UDMA support due a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * missing resistor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static const struct dmi_system_id udma_quirk_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.ident = "Bachmann electronic OT200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			DMI_MATCH(DMI_SYS_VENDOR, "Bachmann electronic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			DMI_MATCH(DMI_PRODUCT_NAME, "OT200"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			DMI_MATCH(DMI_PRODUCT_VERSION, "1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (unlikely(use_msr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		u32 dummy __maybe_unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		rdmsr(MSR_IDE_CFG + reg, *val, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int cs5536_write(struct pci_dev *pdev, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (unlikely(use_msr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		wrmsr(MSR_IDE_CFG + reg, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void cs5536_program_dtc(struct ata_device *adev, u8 tim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct pci_dev *pdev = to_pci_dev(adev->link->ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int dshift = adev->devno ? IDE_D1_SHIFT : IDE_D0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u32 dtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	cs5536_read(pdev, DTC, &dtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	dtc &= ~(IDE_DRV_MASK << dshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	dtc |= tim << dshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	cs5536_write(pdev, DTC, dtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  *	cs5536_cable_detect	-	detect cable type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *	@ap: Port to detect on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  *	Perform cable detection for ATA66 capable cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *	Returns a cable type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int cs5536_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	cs5536_read(pdev, CFG, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (cfg & IDE_CFG_CABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  *	cs5536_set_piomode		-	PIO setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  *	@adev: device on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void cs5536_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	static const u8 drv_timings[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		0x98, 0x55, 0x32, 0x21, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	static const u8 addr_timings[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		0x2, 0x1, 0x0, 0x0, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	static const u8 cmd_timings[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		0x99, 0x92, 0x90, 0x22, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int mode = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	int cmdmode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int cshift = adev->devno ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 cast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (pair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		cmdmode = min(mode, pair->pio_mode - XFER_PIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	cs5536_program_dtc(adev, drv_timings[mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	cs5536_read(pdev, CAST, &cast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	cast &= ~(IDE_CAST_DRV_MASK << cshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	cast |= addr_timings[mode] << cshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	cast |= cmd_timings[cmdmode] << IDE_CAST_CMD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	cs5536_write(pdev, CAST, cast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  *	cs5536_set_dmamode		-	DMA timing setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  *	@adev: Device being configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void cs5536_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	static const u8 udma_timings[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	static const u8 mwdma_timings[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		0x67, 0x21, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u32 etc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	int mode = adev->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int dshift = adev->devno ? IDE_D1_SHIFT : IDE_D0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	cs5536_read(pdev, ETC, &etc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (mode >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		etc &= ~(IDE_DRV_MASK << dshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		etc |= udma_timings[mode - XFER_UDMA_0] << dshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	} else { /* MWDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		etc &= ~(IDE_ETC_UDMA_MASK << dshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		cs5536_program_dtc(adev, mwdma_timings[mode - XFER_MW_DMA_0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	cs5536_write(pdev, ETC, etc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct scsi_host_template cs5536_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct ata_port_operations cs5536_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.inherits		= &ata_bmdma32_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.cable_detect		= cs5536_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.set_piomode		= cs5536_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.set_dmamode		= cs5536_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  *	cs5536_init_one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  *	@dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  *	@id: Entry in match table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		.port_ops = &cs5536_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	static const struct ata_port_info no_udma_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.port_ops = &cs5536_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	const struct ata_port_info *ppi[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (dmi_check_system(udma_quirk_dmi_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		ppi[0] = &no_udma_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		ppi[0] = &info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ppi[1] = &ata_dummy_port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (use_msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		printk(KERN_ERR DRV_NAME ": Using MSR regs instead of PCI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	cs5536_read(dev, CFG, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if ((cfg & IDE_CFG_CHANEN) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		printk(KERN_ERR DRV_NAME ": disabled by BIOS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return ata_pci_bmdma_init_one(dev, ppi, &cs5536_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct pci_device_id cs5536[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_DEV_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct pci_driver cs5536_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.id_table	= cs5536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.probe		= cs5536_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.remove		= ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.suspend	= ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.resume		= ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) module_pci_driver(cs5536_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_AUTHOR("Martin K. Petersen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_DEVICE_TABLE(pci, cs5536);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_VERSION(DRV_VERSION);