Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * pata-cs5535.c 	- CS5535 PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *			  (C) 2005-2006 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *			  Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * and Alexander Kiausch <alex.kiausch@t-online.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Loosely based on the piix & svwks drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *	Available from AMD web site.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *	Review errata to see if serializing is necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DRV_NAME	"pata_cs5535"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DRV_VERSION	"0.2.12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *	The Geode (Aka Athlon GX now) uses an internal MSR based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *	bus system for control. Demented but there you go.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MSR_ATAC_BASE    	0x51300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ATAC_GLD_MSR_CAP 	(MSR_ATAC_BASE+0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ATAC_GLD_MSR_CONFIG    (MSR_ATAC_BASE+0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ATAC_GLD_MSR_SMI       (MSR_ATAC_BASE+0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ATAC_GLD_MSR_ERROR     (MSR_ATAC_BASE+0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ATAC_GLD_MSR_PM        (MSR_ATAC_BASE+0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ATAC_GLD_MSR_DIAG      (MSR_ATAC_BASE+0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ATAC_IO_BAR            (MSR_ATAC_BASE+0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ATAC_RESET             (MSR_ATAC_BASE+0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ATAC_CH0D0_PIO         (MSR_ATAC_BASE+0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ATAC_CH0D0_DMA         (MSR_ATAC_BASE+0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ATAC_CH0D1_PIO         (MSR_ATAC_BASE+0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ATAC_CH0D1_DMA         (MSR_ATAC_BASE+0x23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define ATAC_PCI_ABRTERR       (MSR_ATAC_BASE+0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ATAC_BM0_CMD_PRIM      0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ATAC_BM0_STS_PRIM      0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define ATAC_BM0_PRD           0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CS5535_CABLE_DETECT    0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *	cs5535_cable_detect	-	detect cable type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  *	@ap: Port to detect on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *	Perform cable detection for ATA66 capable cable. Return a libata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  *	cable type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static int cs5535_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u8 cable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (cable & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *	cs5535_set_piomode		-	PIO setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  *	@adev: device on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  *	Set our PIO requirements. The CS5535 is pretty clean about all this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	static const u16 pio_timings[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	static const u16 pio_cmd_timings[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 reg, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int mode = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int cmdmode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* Command timing has to be for the lowest of the pair of devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		int pairmode = pair->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		cmdmode = min(mode, pairmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		/* Write the other drive timing register if it changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (cmdmode < pairmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				pio_cmd_timings[cmdmode] << 16 | pio_timings[pairmode], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* Write the drive timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		pio_cmd_timings[cmdmode] << 16 | pio_timings[mode], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* Set the PIO "format 1" bit in the DMA timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  *	cs5535_set_dmamode		-	DMA timing setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *	@adev: Device being configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	static const u32 udma_timings[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	static const u32 mwdma_timings[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		0x7F0FFFF3, 0x7F035352, 0x7F024241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32 reg, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int mode = adev->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	reg &= 0x80000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (mode >= XFER_UDMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		reg |= udma_timings[mode - XFER_UDMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		reg |= mwdma_timings[mode - XFER_MW_DMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct scsi_host_template cs5535_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct ata_port_operations cs5535_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.inherits	= &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.cable_detect	= cs5535_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.set_piomode	= cs5535_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.set_dmamode	= cs5535_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  *	cs5535_init_one		-	Initialise a CS5530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  *	@dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  *	@id: Entry in match table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  *	Install a driver for the newly found CS5530 companion chip. Most of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *	this is just housekeeping. We have to set the chip up correctly and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *	turn off various bits of emulation magic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.port_ops = &cs5535_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return ata_pci_bmdma_init_one(dev, ppi, &cs5535_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct pci_device_id cs5535[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct pci_driver cs5535_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.id_table	= cs5535,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.probe 		= cs5535_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.remove		= ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.suspend	= ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.resume		= ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) module_pci_driver(cs5535_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MODULE_DESCRIPTION("low-level driver for the NS/AMD 5535");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MODULE_DEVICE_TABLE(pci, cs5535);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MODULE_VERSION(DRV_VERSION);