Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * pata-cs5530.c 	- CS5530 PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *			  (C) 2005 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * based upon cs5530.c by Mark Lord.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Loosely based on the piix & svwks drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *	Available from AMD web site.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DRV_NAME	"pata_cs5530"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DRV_VERSION	"0.7.4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static void __iomem *cs5530_port_base(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *	cs5530_set_piomode		-	PIO setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *	@adev: device on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *	Set our PIO requirements. This is fairly simple on the CS5530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *	chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	static const unsigned int cs5530_pio_timings[2][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	void __iomem *base = cs5530_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* Find out which table to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	tuning = ioread32(base + 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	format = (tuning & 0x80000000UL) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/* Now load the right timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if (adev->devno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		base += 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *	cs5530_set_dmamode		-	DMA timing setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *	@adev: Device being configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *	We cannot mix MWDMA and UDMA without reloading timings each switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *	master to slave. We track the last DMA setup in order to minimise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *	reloads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	void __iomem *base = cs5530_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 tuning, timing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* Find out which table to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	tuning = ioread32(base + 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	switch(adev->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		case XFER_UDMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			timing  = 0x00921250;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		case XFER_UDMA_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			timing  = 0x00911140;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		case XFER_UDMA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			timing  = 0x00911030;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		case XFER_MW_DMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			timing  = 0x00077771;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		case XFER_MW_DMA_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			timing  = 0x00012121;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		case XFER_MW_DMA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			timing  = 0x00002020;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* Merge in the PIO format bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	timing |= (tuning & 0x80000000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (adev->devno == 0) /* Master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		iowrite32(timing, base + 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		if (timing & 0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			tuning |= 0x00100000;	/* UDMA for both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			tuning &= ~0x00100000;	/* MWDMA for both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		iowrite32(tuning, base + 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		iowrite32(timing, base + 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* Set the DMA capable bit in the BMDMA area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	reg |= (1 << (5 + adev->devno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/* Remember the last DMA setup we did */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ap->private_data = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *	cs5530_qc_issue		-	command issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *	@qc: command pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  *	Called when the libata layer is about to issue a command. We wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *	this interface so that we can load the correct ATA timings if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *	necessary.  Specifically we have a problem that there is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *	one MWDMA/UDMA bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static unsigned int cs5530_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct ata_device *prev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/* See if the DMA settings could be wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (ata_dma_enabled(adev) && adev != prev && prev != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		/* Maybe, but do the channels match MWDMA/UDMA ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		if ((ata_using_udma(adev) && !ata_using_udma(prev)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		    (ata_using_udma(prev) && !ata_using_udma(adev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		    	/* Switch the mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		    	cs5530_set_dmamode(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return ata_bmdma_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct scsi_host_template cs5530_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.sg_tablesize	= LIBATA_DUMB_MAX_PRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct ata_port_operations cs5530_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.inherits	= &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.qc_prep 	= ata_bmdma_dumb_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.qc_issue	= cs5530_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.cable_detect	= ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.set_piomode	= cs5530_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.set_dmamode	= cs5530_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct dmi_system_id palmax_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.ident = "Palmax PD1100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int cs5530_is_palmax(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (dmi_check_system(palmax_dmi_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  *	cs5530_init_chip	-	Chipset init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  *	Perform the chip initialisation work that is shared between both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  *	setup and resume paths
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int cs5530_init_chip(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct pci_dev *master_0 = NULL, *cs5530_0 = NULL, *dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				master_0 = pci_dev_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				cs5530_0 = pci_dev_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (!master_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		goto fail_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (!cs5530_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		goto fail_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	pci_set_master(cs5530_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	pci_try_set_mwi(cs5530_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * Set PCI CacheLineSize to 16-bytes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 * Note: This value is constant because the 5530 is only a Geode companion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * Disable trapping of UDMA register accesses (Win98 hack):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	pci_write_config_word(cs5530_0, 0xd0, 0x5006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * The other settings are what is necessary to get the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * into a sane state for IDE DMA operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	pci_write_config_byte(master_0, 0x40, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * Set max PCI burst size (16-bytes seems to work best):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 *	   16bytes: set bit-1 at 0x41 (reg value of 0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 *	all others: clear bit-1 at 0x41, and do:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 *	  128bytes: OR 0x00 at 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 *	  256bytes: OR 0x04 at 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 *	  512bytes: OR 0x08 at 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 *	 1024bytes: OR 0x0c at 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	pci_write_config_byte(master_0, 0x41, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * These settings are necessary to get the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * into a sane state for IDE DMA operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	pci_write_config_byte(master_0, 0x42, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	pci_write_config_byte(master_0, 0x43, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	pci_dev_put(master_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	pci_dev_put(cs5530_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) fail_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	pci_dev_put(master_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	pci_dev_put(cs5530_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  *	cs5530_init_one		-	Initialise a CS5530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  *	@dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  *	@id: Entry in match table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  *	Install a driver for the newly found CS5530 companion chip. Most of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  *	this is just housekeeping. We have to set the chip up correctly and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  *	turn off various bits of emulation magic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.port_ops = &cs5530_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	/* The docking connector doesn't do UDMA, and it seems not MWDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	static const struct ata_port_info info_palmax_secondary = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.port_ops = &cs5530_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	const struct ata_port_info *ppi[] = { &info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/* Chip initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (cs5530_init_chip())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (cs5530_is_palmax())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		ppi[1] = &info_palmax_secondary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	/* Now kick off ATA set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return ata_pci_bmdma_init_one(pdev, ppi, &cs5530_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int cs5530_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/* If we fail on resume we are doomed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (cs5530_init_chip())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const struct pci_device_id cs5530[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct pci_driver cs5530_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.name 		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.id_table	= cs5530,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.probe 		= cs5530_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.remove		= ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.suspend	= ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.resume		= cs5530_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) module_pci_driver(cs5530_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MODULE_DEVICE_TABLE(pci, cs5530);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MODULE_VERSION(DRV_VERSION);