^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_cmd64x.c - CMD64x PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) 2005 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) 2009-2010 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) 2012 MontaVista Software, LLC <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Note, this driver is not used at all on other systems because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * there the "BIOS" has done all of the following already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Due to massive hardware bugs, UltraDMA is only supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * on the 646U2 and not on the 646U.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright (C) 1998 David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Testing work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRV_NAME "pata_cmd64x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRV_VERSION "0.2.18"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * CMD64x specific registers definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) CFR = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CFR_INTR_CH0 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CNTRL = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CNTRL_CH0 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CNTRL_CH1 = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CMDTIM = 0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ARTTIM0 = 0x53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DRWTIM0 = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ARTTIM1 = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DRWTIM1 = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ARTTIM23 = 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ARTTIM23_DIS_RA2 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ARTTIM23_DIS_RA3 = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ARTTIM23_INTR_CH1 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DRWTIM2 = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) BRST = 0x59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DRWTIM3 = 0x5b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) BMIDECR0 = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MRDMODE = 0x71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MRDMODE_INTR_CH0 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MRDMODE_INTR_CH1 = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) BMIDESR0 = 0x72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) UDIDETCR0 = 0x73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DTPR0 = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) BMIDECR1 = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) BMIDECSR = 0x79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) UDIDETCR1 = 0x7B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DTPR1 = 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int cmd648_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Check cable detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pci_read_config_byte(pdev, BMIDECSR, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (r & (1 << ap->port_no))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * cmd64x_set_timing - set PIO and MWDMA timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @mode: mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Called to do the PIO and MWDMA mode setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const unsigned long T = 1000000 / 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Port layout is not logical so use a table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const u8 arttim_port[2][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { ARTTIM0, ARTTIM1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { ARTTIM23, ARTTIM23 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const u8 drwtim_port[2][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { DRWTIM0, DRWTIM1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { DRWTIM2, DRWTIM3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int arttim = arttim_port[ap->port_no][adev->devno];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int drwtim = drwtim_port[ap->port_no][adev->devno];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* ata_timing_compute is smart and will produce timings for MWDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) that don't violate the drives PIO capabilities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ap->port_no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Slave has shared address setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct ata_timing tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) t.active, t.recover, t.setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (t.recover > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) t.active += t.recover - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) t.recover = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (t.active > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) t.active = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Now convert the clocks into values we can actually stuff into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (t.recover == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) t.recover = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) else if (t.recover > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) t.recover--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) t.recover = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (t.setup > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) t.setup = 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) t.setup = setup_data[t.setup];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) t.active &= 0x0F; /* 0 = 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Load setup timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pci_read_config_byte(pdev, arttim, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) reg &= 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) reg |= t.setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pci_write_config_byte(pdev, arttim, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Load active/recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * cmd64x_set_piomode - set initial PIO mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Used when configuring the devices ot set the PIO timings. All the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * actual work is done by the PIO/MWDMA setting helper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) cmd64x_set_timing(ap, adev, adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * cmd64x_set_dmamode - set initial DMA mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Called to do the DMA mode setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const u8 udma_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0x30, 0x20, 0x10, 0x20, 0x10, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 regU, regD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int pciU = UDIDETCR0 + 8 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int pciD = BMIDESR0 + 8 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int shift = 2 * adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pci_read_config_byte(pdev, pciD, ®D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pci_read_config_byte(pdev, pciU, ®U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* DMA bits off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) regD &= ~(0x20 << adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* DMA control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regU &= ~(0x30 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* DMA timing bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) regU &= ~(0x05 << adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (adev->dma_mode >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Merge the timing value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Merge the control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) regU |= 1 << adev->devno; /* UDMA on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) regU |= 4 << adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) regU &= ~ (1 << adev->devno); /* UDMA off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cmd64x_set_timing(ap, adev, adev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) regD |= 0x20 << adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pci_write_config_byte(pdev, pciU, regU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pci_write_config_byte(pdev, pciD, regD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * cmd64x_sff_irq_check - check IDE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Check IDE interrupt in CFR/ARTTIM23 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static bool cmd64x_sff_irq_check(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int irq_reg = ap->port_no ? ARTTIM23 : CFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* NOTE: reading the register should clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pci_read_config_byte(pdev, irq_reg, &irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return irq_stat & irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * cmd64x_sff_irq_clear - clear IDE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void cmd64x_sff_irq_clear(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int irq_reg = ap->port_no ? ARTTIM23 : CFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ata_bmdma_irq_clear(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Reading the register should be enough to clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pci_read_config_byte(pdev, irq_reg, &irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * cmd648_sff_irq_check - check IDE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Check IDE interrupt in MRDMODE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static bool cmd648_sff_irq_check(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned long base = pci_resource_start(pdev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 mrdmode = inb(base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return mrdmode & irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * cmd648_sff_irq_clear - clear IDE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Clear IDE interrupt in MRDMODE and DMA status registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void cmd648_sff_irq_clear(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long base = pci_resource_start(pdev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 mrdmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ata_bmdma_irq_clear(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Clear this port's interrupt bit (leaving the other port alone) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mrdmode = inb(base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mrdmode &= ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) outb(mrdmode | irq_mask, base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * cmd646r1_bmdma_stop - DMA stop callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @qc: Command in progress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Stub for now while investigating the r1 quirk in the old driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ata_bmdma_stop(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct scsi_host_template cmd64x_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct ata_port_operations cmd64x_base_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .set_piomode = cmd64x_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .set_dmamode = cmd64x_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct ata_port_operations cmd64x_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .inherits = &cmd64x_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .sff_irq_check = cmd64x_sff_irq_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .sff_irq_clear = cmd64x_sff_irq_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static struct ata_port_operations cmd646r1_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .inherits = &cmd64x_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .sff_irq_check = cmd64x_sff_irq_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .sff_irq_clear = cmd64x_sff_irq_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .bmdma_stop = cmd646r1_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct ata_port_operations cmd646r3_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .inherits = &cmd64x_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .sff_irq_check = cmd648_sff_irq_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .sff_irq_clear = cmd648_sff_irq_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct ata_port_operations cmd648_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .inherits = &cmd64x_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .sff_irq_check = cmd648_sff_irq_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .sff_irq_clear = cmd648_sff_irq_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .cable_detect = cmd648_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void cmd64x_fixup(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 mrdmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pci_read_config_byte(pdev, MRDMODE, &mrdmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mrdmode &= ~0x30; /* IRQ set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mrdmode |= 0x02; /* Memory read line enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pci_write_config_byte(pdev, MRDMODE, mrdmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* PPC specific fixup copied from old driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #ifdef CONFIG_PPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct ata_port_info cmd_info[7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { /* CMD 643 - no UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .port_ops = &cmd64x_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { /* CMD 646 with broken UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .port_ops = &cmd64x_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { /* CMD 646U with broken UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .port_ops = &cmd646r3_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { /* CMD 646U2 with working UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .port_ops = &cmd646r3_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { /* CMD 646 rev 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .port_ops = &cmd646r1_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { /* CMD 648 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .port_ops = &cmd648_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { /* CMD 649 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .port_ops = &cmd648_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) const struct ata_port_info *ppi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) &cmd_info[id->driver_data],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &cmd_info[id->driver_data],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct pci_dev *bridge = pdev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* mobility split bridges don't report enabled ports correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int port_ok = !(bridge && bridge->vendor ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int cntrl_ch0_ok = (id->driver_data != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (id->driver_data == 0) /* 643 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ata_pci_bmdma_clear_simplex(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (pdev->device == PCI_DEVICE_ID_CMD_646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) switch (pdev->revision) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* UDMA works since rev 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ppi[0] = &cmd_info[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ppi[1] = &cmd_info[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Interrupts in MRDMODE since rev 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ppi[0] = &cmd_info[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ppi[1] = &cmd_info[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Rev 1 with other problems? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ppi[0] = &cmd_info[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ppi[1] = &cmd_info[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Early revs have no CNTRL_CH0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) cntrl_ch0_ok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) cmd64x_fixup(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* check for enabled ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pci_read_config_byte(pdev, CNTRL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!port_ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_notice(&pdev->dev, "Primary port is disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ppi[0] = &ata_dummy_port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (port_ok && !(reg & CNTRL_CH1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_notice(&pdev->dev, "Secondary port is disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ppi[1] = &ata_dummy_port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int cmd64x_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) cmd64x_fixup(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct pci_device_id cmd64x[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static struct pci_driver cmd64x_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .id_table = cmd64x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .probe = cmd64x_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .resume = cmd64x_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) module_pci_driver(cmd64x_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_DEVICE_TABLE(pci, cmd64x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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