^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_cmd640.c - CMD640 PCI PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) 2007 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * linux/drivers/ide/pci/cmd640.c Version 1.02 Sep 01, 1996
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1995-1996 Linus Torvalds & authors (see driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This drives only the PCI version of the controller. If you have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * VLB one then we have enough docs to support it but you can write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * your own code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRV_NAME "pata_cmd640"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRV_VERSION "0.0.5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct cmd640_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 reg58[ATA_MAX_DEVICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CFR = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CNTRL = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CMDTIM = 0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ARTIM0 = 0x53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DRWTIM0 = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ARTIM23 = 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DRWTIM23 = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) BRST = 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * cmd640_set_piomode - set initial PIO mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Called to do the PIO mode setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void cmd640_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct cmd640_reg *timing = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const unsigned long T = 1000000 / 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int arttim = ARTIM0 + 2 * adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* The second channel has shared timings and the setup timing is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) messy to switch to merge it for worst case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (ap->port_no && pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct ata_timing p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Make the timings fit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (t.recover > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) t.active += t.recover - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) t.recover = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (t.active > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) t.active = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Now convert the clocks into values we can actually stuff into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (t.recover > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) t.recover--; /* 640B only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) t.recover = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (t.setup > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) t.setup = 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) t.setup = setup_data[t.setup];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (ap->port_no == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) t.active &= 0x0F; /* 0 = 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Load setup timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pci_read_config_byte(pdev, arttim, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg &= 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg |= t.setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pci_write_config_byte(pdev, arttim, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Load active/recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pci_write_config_byte(pdev, arttim + 1, (t.active << 4) | t.recover);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Save the shared timings for channel, they will be loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) by qc_issue. Reloading the setup time is expensive so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) keep a merged one loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pci_read_config_byte(pdev, ARTIM23, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) reg &= 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg |= t.setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pci_write_config_byte(pdev, ARTIM23, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) timing->reg58[adev->devno] = (t.active << 4) | t.recover;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * cmd640_qc_issue - command preparation hook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @qc: Command to be issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Channel 1 has shared timings. We must reprogram the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * clock each drive 2/3 switch we do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static unsigned int cmd640_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct cmd640_reg *timing = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ap->port_no != 0 && adev->devno != timing->last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) timing->last = adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ata_sff_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * cmd640_port_start - port setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @ap: ATA port being set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * The CMD640 needs to maintain private data structures so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * allocate space here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int cmd640_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct cmd640_reg *timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (timing == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) timing->last = -1; /* Force a load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ap->private_data = timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static bool cmd640_sff_irq_check(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int irq_reg = ap->port_no ? ARTIM23 : CFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 irq_stat, irq_mask = ap->port_no ? 0x10 : 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pci_read_config_byte(pdev, irq_reg, &irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return irq_stat & irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct scsi_host_template cmd640_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ATA_PIO_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct ata_port_operations cmd640_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .inherits = &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* In theory xfer_noirq is not needed once we kill the prefetcher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .sff_data_xfer = ata_sff_data_xfer32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .sff_irq_check = cmd640_sff_irq_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .qc_issue = cmd640_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .set_piomode = cmd640_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .port_start = cmd640_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void cmd640_hardware_init(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* CMD640 detected, commiserations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pci_write_config_byte(pdev, 0x5B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* PIO0 command cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pci_write_config_byte(pdev, CMDTIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* 512 byte bursts (sector) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pci_write_config_byte(pdev, BRST, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * A reporter a long time ago
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Had problems with the data fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * So don't run the risk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Of putting crap on the disk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * For its better just to go slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Do channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pci_read_config_byte(pdev, CNTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pci_write_config_byte(pdev, CNTRL, ctrl | 0xC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Ditto for channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pci_read_config_byte(pdev, ARTIM23, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ctrl |= 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pci_write_config_byte(pdev, ARTIM23, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int cmd640_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .port_ops = &cmd640_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const struct ata_port_info *ppi[] = { &info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cmd640_hardware_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ata_pci_sff_init_one(pdev, ppi, &cmd640_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int cmd640_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cmd640_hardware_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct pci_device_id cmd640[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { PCI_VDEVICE(CMD, 0x640), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct pci_driver cmd640_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .id_table = cmd640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .probe = cmd640_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .resume = cmd640_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) module_pci_driver(cmd640_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_DESCRIPTION("low-level driver for CMD640 PATA controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_DEVICE_TABLE(pci, cmd640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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