^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Palmchip BK3710 PATA controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2017 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on palm_bk3710.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRV_NAME "pata_bk3710"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BK3710_TF_OFFSET 0x1F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BK3710_CTL_OFFSET 0x3F6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BK3710_BMISP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BK3710_IDETIMP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BK3710_UDMACTL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BK3710_MISCCTL 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BK3710_REGSTB 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BK3710_REGRCVR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BK3710_DATSTB 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BK3710_DATRCVR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BK3710_DMASTB 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BK3710_DMARCVR 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BK3710_UDMASTB 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BK3710_UDMATRP 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BK3710_UDMAENV 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BK3710_IORDYTMP 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct scsi_host_template pata_bk3710_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static unsigned int ideclk_period; /* in nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct pata_bk3710_udmatiming {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* tENV is always a minimum of 20 nsec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { 160, 240 / 2 }, /* UDMA Mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 125, 160 / 2 }, /* UDMA Mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 100, 120 / 2 }, /* UDMA Mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { 100, 90 / 2 }, /* UDMA Mode 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { 100, 60 / 2 }, /* UDMA Mode 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { 85, 40 / 2 }, /* UDMA Mode 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u16 val16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 tenv, trp, t0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* DMA Data Setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ideclk_period) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ideclk_period) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* udmastb Ultra DMA Access Strobe Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) val32 |= t0 << (dev ? 8 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) iowrite32(val32, base + BK3710_UDMASTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* udmatrp Ultra DMA Ready to Pause Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val32 |= trp << (dev ? 8 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) iowrite32(val32, base + BK3710_UDMATRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* udmaenv Ultra DMA envelop Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val32 |= tenv << (dev ? 8 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) iowrite32(val32, base + BK3710_UDMAENV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Enable UDMA for Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) iowrite16(val16, base + BK3710_UDMACTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned short min_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const struct ata_timing *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int cycletime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 val16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 td, tkw, t0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) t = ata_timing_find_mode(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cycletime = max_t(int, t->cycle, min_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* DMA Data Setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) t0 = DIV_ROUND_UP(cycletime, ideclk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) td = DIV_ROUND_UP(t->active, ideclk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) tkw = t0 - td - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) td--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val32 |= td << (dev ? 8 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) iowrite32(val32, base + BK3710_DMASTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val32 |= tkw << (dev ? 8 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) iowrite32(val32, base + BK3710_DMARCVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Disable UDMA for Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) iowrite16(val16, base + BK3710_UDMACTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void pata_bk3710_set_dmamode(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int is_slave = adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const u8 xferspeed = adev->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (xferspeed >= XFER_UDMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pata_bk3710_setudmamode(base, is_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) xferspeed - XFER_UDMA_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pata_bk3710_setmwdmamode(base, is_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) adev->id[ATA_ID_EIDE_DMA_MIN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) xferspeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int dev, unsigned int cycletime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const struct ata_timing *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 t2, t2i, t0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) t = ata_timing_find_mode(XFER_PIO_0 + mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* PIO Data Setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) t0 = DIV_ROUND_UP(cycletime, ideclk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) t2 = DIV_ROUND_UP(t->active, ideclk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) t2i = t0 - t2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) t2--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val32 |= t2 << (dev ? 8 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) iowrite32(val32, base + BK3710_DATSTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val32 |= t2i << (dev ? 8 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) iowrite32(val32, base + BK3710_DATRCVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* FIXME: this is broken also in the old driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 mode2 = pair->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (mode2 < mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) mode = mode2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* TASKFILE Setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) t2i = t0 - t2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) t2--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) val32 |= t2 << (dev ? 8 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) iowrite32(val32, base + BK3710_REGSTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val32 |= t2i << (dev ? 8 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) iowrite32(val32, base + BK3710_REGRCVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void pata_bk3710_set_piomode(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const u16 *id = adev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int cycle_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int is_slave = adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const u8 pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (id[ATA_ID_FIELD_VALID] & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ata_id_has_iordy(id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cycle_time = id[ATA_ID_EIDE_PIO_IORDY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cycle_time = id[ATA_ID_EIDE_PIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* conservative "downgrade" for all pre-ATA2 drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (pio < 3 && cycle_time < t->cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cycle_time = 0; /* use standard timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!cycle_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cycle_time = t->cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void pata_bk3710_chipinit(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * REVISIT: the ATA reset signal needs to be managed through a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * GPIO, which means it should come from platform_data. Until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * we get and use such information, we have to trust that things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * have been reset before we get here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Program the IDETIMP Register Value based on the following assumptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * (ATA_IDETIMP_IDEEN , ENABLE ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * (ATA_IDETIMP_PREPOST1 , DISABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * (ATA_IDETIMP_PREPOST0 , DISABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * DM6446 silicon rev 2.1 and earlier have no observed net benefit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * from enabling prefetch/postwrite.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) iowrite16(BIT(15), base + BK3710_IDETIMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * UDMACTL Ultra-ATA DMA Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * (ATA_UDMACTL_UDMAP1 , 0 ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * (ATA_UDMACTL_UDMAP0 , 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) iowrite16(0, base + BK3710_UDMACTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * MISCCTL Miscellaneous Conrol Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * (ATA_MISCCTL_HWNHLD1P , 1 cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * (ATA_MISCCTL_HWNHLD0P , 1 cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * (ATA_MISCCTL_TIMORIDE , 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) iowrite32(0x001, base + BK3710_MISCCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * IORDYTMP IORDY Timer for Primary Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * (ATA_IORDYTMP_IORDYTMP , DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) iowrite32(0, base + BK3710_IORDYTMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Configure BMISP Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * (ATA_BMISP_DMAEN1 , DISABLE ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * (ATA_BMISP_DMAEN0 , DISABLE ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * (ATA_BMISP_IORDYINT , CLEAR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * (ATA_BMISP_INTRSTAT , CLEAR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * (ATA_BMISP_DMAERROR , CLEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) iowrite16(0xE, base + BK3710_BMISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pata_bk3710_setpiomode(base, NULL, 0, 600, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pata_bk3710_setpiomode(base, NULL, 1, 600, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct ata_port_operations pata_bk3710_ports_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .cable_detect = ata_cable_80wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .set_piomode = pata_bk3710_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .set_dmamode = pata_bk3710_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int __init pata_bk3710_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* NOTE: round *down* to meet minimum timings; we count in clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ideclk_period = 1000000000UL / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pr_err(DRV_NAME ": failed to get IRQ resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) base = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* configure the Palmchip controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pata_bk3710_chipinit(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* allocate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) host = ata_host_alloc(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ap->ops = &pata_bk3710_ports_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ap->pio_mask = ATA_PIO4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ap->mwdma_mask = ATA_MWDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ap->flags |= ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ap->ioaddr.data_addr = base + BK3710_TF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ap->ioaddr.error_addr = base + BK3710_TF_OFFSET + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ap->ioaddr.feature_addr = base + BK3710_TF_OFFSET + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ap->ioaddr.nsect_addr = base + BK3710_TF_OFFSET + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ap->ioaddr.lbal_addr = base + BK3710_TF_OFFSET + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ap->ioaddr.lbam_addr = base + BK3710_TF_OFFSET + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ap->ioaddr.lbah_addr = base + BK3710_TF_OFFSET + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ap->ioaddr.device_addr = base + BK3710_TF_OFFSET + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ap->ioaddr.status_addr = base + BK3710_TF_OFFSET + 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ap->ioaddr.command_addr = base + BK3710_TF_OFFSET + 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ap->ioaddr.altstatus_addr = base + BK3710_CTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ap->ioaddr.ctl_addr = base + BK3710_CTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ap->ioaddr.bmdma_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (unsigned long)base + BK3710_TF_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) (unsigned long)base + BK3710_CTL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* activate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ata_host_activate(host, irq, ata_sff_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) &pata_bk3710_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_ALIAS("platform:palm_bk3710");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static struct platform_driver pata_bk3710_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .name = "palm_bk3710",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int __init pata_bk3710_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) module_init(pata_bk3710_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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