^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_artop.c - ARTOP ATA controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) 2006 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) 2007,2011 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based in part on drivers/ide/pci/aec62xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 865/865R fixes for Macintosh card version from a patch to the old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * driver by Thibaut VARENE <varenet@parisc-linux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * When setting the PCI latency we must set 0x80 or higher for burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * performance Alessandro Zummo <alessandro.zummo@towertech.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Investigate no_dsc on 850R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Clock detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRV_NAME "pata_artop"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRV_VERSION "0.4.6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * get PCI bus speed functionality we leave this as 0. Its a variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * for when we get the functionality and also for folks wanting to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * test stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * artop62x0_pre_reset - probe begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @link: link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Nothing complicated needed here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct pci_bits artop_enable_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Odd numbered device ids are the units with enable bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if ((pdev->device & 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * artop6260_cable_detect - identify cable type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @ap: Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Identify the cable type for the ARTOP interface in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int artop6260_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pci_read_config_byte(pdev, 0x49, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (tmp & (1 << ap->port_no))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * artop6210_load_piomode - Load a set of PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @adev: Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @pio: PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Set PIO mode for device, in host controller PCI config space. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * is used both to set PIO timings in PIO mode and also to set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * matching PIO clocking for UDMA, as well as the MWDMA timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int dn = adev->devno + 2 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const u16 timing[2][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Load the PIO timing active/recovery bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * artop6210_set_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @adev: Device we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Set PIO mode for device, in host controller PCI config space. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * the event UDMA is used the later call to set_dmamode will set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * bits as required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int dn = adev->devno + 2 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 ultra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pci_read_config_byte(pdev, 0x54, &ultra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ultra &= ~(3 << (2 * dn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pci_write_config_byte(pdev, 0x54, ultra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * artop6260_load_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @adev: Device we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @pio: PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Set PIO mode for device, in host controller PCI config space. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * ARTOP6260 and relatives store the timing data differently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int dn = adev->devno + 2 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const u8 timing[2][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0x00, 0x0A, 0x08, 0x33, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 0x70, 0x7A, 0x78, 0x43, 0x41 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Load the PIO timing active/recovery bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * artop6260_set_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @adev: Device we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Set PIO mode for device, in host controller PCI config space. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * the event UDMA is used the later call to set_dmamode will set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * bits as required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 ultra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * artop6210_set_dmamode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @adev: Device whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Set DMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int dn = adev->devno + 2 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 ultra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (adev->dma_mode == XFER_MW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pio = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Load the PIO timing active/recovery bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) artop6210_load_piomode(ap, adev, pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pci_read_config_byte(pdev, 0x54, &ultra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ultra &= ~(3 << (2 * dn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Add ultra DMA bits if in UDMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (adev->dma_mode >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (mode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ultra |= (mode << (2 * dn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pci_write_config_byte(pdev, 0x54, ultra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * artop6260_set_dmamode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @adev: Device we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Set DMA mode for device, in host controller PCI config space. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * ARTOP6260 and relatives store the timing data differently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 ultra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (adev->dma_mode == XFER_MW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pio = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Load the PIO timing active/recovery bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) artop6260_load_piomode(ap, adev, pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Add ultra DMA bits if in UDMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (adev->dma_mode >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (mode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ultra |= (mode << (4 * adev->devno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * artop_6210_qc_defer - implement serialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @qc: command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Issue commands per host on this chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int artop6210_qc_defer(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct ata_host *host = qc->ap->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* First apply the usual rules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rc = ata_std_qc_defer(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Now apply serialization rules. Only allow a command if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) other channel state machine is idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (alt && alt->qc_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ATA_DEFER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static struct scsi_host_template artop_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct ata_port_operations artop6210_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .set_piomode = artop6210_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .set_dmamode = artop6210_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .prereset = artop62x0_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .qc_defer = artop6210_qc_defer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct ata_port_operations artop6260_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .cable_detect = artop6260_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .set_piomode = artop6260_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .set_dmamode = artop6260_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .prereset = artop62x0_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void atp8xx_fixup(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (pdev->device == 0x0005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* BIOS may have left us in UDMA, clear it before libata probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pci_write_config_byte(pdev, 0x54, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) else if (pdev->device == 0x0008 || pdev->device == 0x0009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Mac systems come up with some registers not set as we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) will need them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Clear reset & test bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pci_read_config_byte(pdev, 0x49, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pci_write_config_byte(pdev, 0x49, reg & ~0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* PCI latency must be > 0x80 for burst mode, tweak it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * if required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (reg <= 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Enable IRQ output and burst mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pci_read_config_byte(pdev, 0x4a, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * artop_init_one - Register ARTOP ATA PCI device with kernel services
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @pdev: PCI device to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @ent: Entry in artop_pci_tbl matching with @pdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Called from kernel PCI layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Inherited from PCI layer (may sleep).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * RETURNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Zero on success, or -ERRNO value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct ata_port_info info_6210 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .port_ops = &artop6210_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct ata_port_info info_626x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .port_ops = &artop6260_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const struct ata_port_info info_628x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .port_ops = &artop6260_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct ata_port_info info_628x_fast = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .port_ops = &artop6260_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) const struct ata_port_info *ppi[] = { NULL, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (id->driver_data == 0) /* 6210 variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ppi[0] = &info_6210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) else if (id->driver_data == 1) /* 6260 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ppi[0] = &info_626x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) else if (id->driver_data == 2) { /* 6280 or 6280 + fast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned long io = pci_resource_start(pdev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ppi[0] = &info_628x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (inb(io) & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ppi[0] = &info_628x_fast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) BUG_ON(ppi[0] == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) atp8xx_fixup(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const struct pci_device_id artop_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { PCI_VDEVICE(ARTOP, 0x0005), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { PCI_VDEVICE(ARTOP, 0x0006), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { PCI_VDEVICE(ARTOP, 0x0007), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { PCI_VDEVICE(ARTOP, 0x0008), 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { PCI_VDEVICE(ARTOP, 0x0009), 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int atp8xx_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) atp8xx_fixup(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct pci_driver artop_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .id_table = artop_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .probe = artop_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .resume = atp8xx_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) module_pci_driver(artop_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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