^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * drivers/ata/pata_arasan_cf.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Arasan Compact Flash host controller source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The Arasan CompactFlash Device Controller IP core has three basic modes of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * operation: PC card ATA using I/O mode, PC card ATA using memory mode, PC card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * ATA using true IDE modes. This driver supports only True IDE mode currently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Arasan CF Controller shares global irq register with Arasan XD Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Tested on arch/arm/mach-spear13xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/pata_arasan_cf_data.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRIVER_NAME "arasan_cf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TIMEOUT msecs_to_jiffies(3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* CompactFlash Interface Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CFI_STS 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STS_CHG (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BIN_AUDIO_OUT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CARD_DETECT1 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CARD_DETECT2 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define INP_ACK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CARD_READY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IO_READY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define B16_IO_PORT_SEL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IRQ_STS 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IRQ_EN 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CARD_DETECT_IRQ (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STATUS_CHNG_IRQ (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MEM_MODE_IRQ (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IO_MODE_IRQ (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TRUE_IDE_MODE_IRQ (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PIO_XFER_ERR_IRQ (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BUF_AVAIL_IRQ (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define XFER_DONE_IRQ (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IGNORED_IRQS (STATUS_CHNG_IRQ | MEM_MODE_IRQ | IO_MODE_IRQ |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) TRUE_IDE_MODE_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TRUE_IDE_IRQS (CARD_DETECT_IRQ | PIO_XFER_ERR_IRQ |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) BUF_AVAIL_IRQ | XFER_DONE_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Operation Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OP_MODE 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CARD_MODE_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MEM_MODE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IO_MODE (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TRUE_IDE_MODE (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CARD_TYPE_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CF_CARD (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CF_PLUS_CARD (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CARD_RESET (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CFHOST_ENB (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OUTPUTS_TRISTATE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ULTRA_DMA_ENB (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MULTI_WORD_DMA_ENB (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DRQ_BLOCK_SIZE_MASK (0x3 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DRQ_BLOCK_SIZE_512 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DRQ_BLOCK_SIZE_1024 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DRQ_BLOCK_SIZE_2048 (2 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DRQ_BLOCK_SIZE_4096 (3 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* CF Interface Clock Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_CFG 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CF_IF_CLK_MASK (0XF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* CF Timing Mode Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TM_CFG 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MEM_MODE_TIMING_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MEM_MODE_TIMING_250NS (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MEM_MODE_TIMING_120NS (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MEM_MODE_TIMING_100NS (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MEM_MODE_TIMING_80NS (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IO_MODE_TIMING_MASK (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IO_MODE_TIMING_250NS (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IO_MODE_TIMING_120NS (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IO_MODE_TIMING_100NS (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IO_MODE_TIMING_80NS (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TRUEIDE_PIO_TIMING_MASK (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TRUEIDE_PIO_TIMING_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TRUEIDE_MWORD_DMA_TIMING_MASK (0x7 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TRUEIDE_MWORD_DMA_TIMING_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ULTRA_DMA_TIMING_MASK (0x7 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ULTRA_DMA_TIMING_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* CF Transfer Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define XFER_ADDR 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define XFER_ADDR_MASK (0x7FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MAX_XFER_COUNT 0x20000u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Transfer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define XFER_CTR 0x01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define XFER_COUNT_MASK (0x3FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ADDR_INC_DISABLE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define XFER_WIDTH_MASK (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define XFER_WIDTH_8B (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define XFER_WIDTH_16B (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MEM_TYPE_MASK (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MEM_TYPE_COMMON (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MEM_TYPE_ATTRIBUTE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MEM_IO_XFER_MASK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MEM_XFER (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IO_XFER (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DMA_XFER_MODE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AHB_BUS_NORMAL_PIO_OPRTN (~(1 << 29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define XFER_DIR_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define XFER_READ (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define XFER_WRITE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define XFER_START (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Write Data Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define WRITE_PORT 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Read Data Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define READ_PORT 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* ATA Data Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ATA_DATA_PORT 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ATA_DATA_PORT_MASK (0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* ATA Error/Features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ATA_ERR_FTR 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* ATA Sector Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ATA_SC 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* ATA Sector Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ATA_SN 0x03C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* ATA Cylinder Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ATA_CL 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* ATA Cylinder High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ATA_CH 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* ATA Select Card/Head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ATA_SH 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* ATA Status-Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ATA_STS_CMD 0x04C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* ATA Alternate Status/Device Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ATA_ASTS_DCTR 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Extended Write Data Port 0x200-0x3FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EXT_WRITE_PORT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Extended Read Data Port 0x400-0x5FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EXT_READ_PORT 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FIFO_SIZE 0x200u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Global Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GIRQ_STS 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Global Interrupt Status enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GIRQ_STS_EN 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Global Interrupt Signal enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GIRQ_SGN_EN 0x808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GIRQ_CF (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GIRQ_XD (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Compact Flash Controller Dev Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct arasan_cf_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* pointer to ata_host structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* clk structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* physical base address of controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dma_addr_t pbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* virtual base address of controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void __iomem *vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* irq number*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* status to be updated to framework regarding DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 dma_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Card is present or Not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 card_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* dma specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Completion for transfer complete interrupt from controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct completion cf_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Completion for DMA transfer complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct completion dma_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Dma channel allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Mask for DMA transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* DMA transfer work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* DMA delayed finish work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct delayed_work dwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* qc to be transferred using DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct ata_queued_cmd *qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct scsi_host_template arasan_cf_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ATA_BASE_SHT(DRIVER_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .dma_boundary = 0xFFFFFFFFUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void cf_dumpregs(struct arasan_cf_dev *acdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct device *dev = acdev->host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_dbg(dev, ": =========== REGISTER DUMP ===========");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_dbg(dev, ": =====================================");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Enable/Disable global interrupts shared between CF and XD ctrlr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void cf_ginterrupt_enable(struct arasan_cf_dev *acdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* enable should be 0 or 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel(enable, acdev->vbase + GIRQ_STS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel(enable, acdev->vbase + GIRQ_SGN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Enable/Disable CF interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) cf_interrupt_enable(struct arasan_cf_dev *acdev, u32 mask, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 val = readl(acdev->vbase + IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* clear & enable/disable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel(mask, acdev->vbase + IRQ_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) writel(val | mask, acdev->vbase + IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) writel(val & ~mask, acdev->vbase + IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline void cf_card_reset(struct arasan_cf_dev *acdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 val = readl(acdev->vbase + OP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writel(val | CARD_RESET, acdev->vbase + OP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) writel(val & ~CARD_RESET, acdev->vbase + OP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static inline void cf_ctrl_reset(struct arasan_cf_dev *acdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) acdev->vbase + OP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) acdev->vbase + OP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct ata_port *ap = acdev->host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct ata_eh_info *ehi = &ap->link.eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 val = readl(acdev->vbase + CFI_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Both CD1 & CD2 should be low if card inserted completely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!(val & (CARD_DETECT1 | CARD_DETECT2))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (acdev->card_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) acdev->card_present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cf_card_reset(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!acdev->card_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) acdev->card_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (hotplugged) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ata_ehi_hotplugged(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int cf_init(struct arasan_cf_dev *acdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int if_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = clk_prepare_enable(acdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_dbg(acdev->host->dev, "clock enable failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = clk_set_rate(acdev->clk, 166000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_warn(acdev->host->dev, "clock set rate failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) clk_disable_unprepare(acdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* configure CF interface clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* TODO: read from device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if_clk = CF_IF_CLK_166M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (pdata && pdata->cf_if_clk <= CF_IF_CLK_200M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if_clk = pdata->cf_if_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) writel(if_clk, acdev->vbase + CLK_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) cf_ginterrupt_enable(acdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void cf_exit(struct arasan_cf_dev *acdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cf_ginterrupt_enable(acdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cf_interrupt_enable(acdev, TRUE_IDE_IRQS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cf_card_reset(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) acdev->vbase + OP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) clk_disable_unprepare(acdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void dma_callback(void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct arasan_cf_dev *acdev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) complete(&acdev->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static inline void dma_complete(struct arasan_cf_dev *acdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct ata_queued_cmd *qc = acdev->qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) acdev->qc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ata_sff_interrupt(acdev->irq, acdev->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ata_ehi_push_desc(&qc->ap->link.eh_info, "DMA Failed: Timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline int wait4buf(struct arasan_cf_dev *acdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!wait_for_completion_timeout(&acdev->cf_completion, TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 rw = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(acdev->host->dev, "%s TimeOut", rw ? "write" : "read");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Check if PIO Error interrupt has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (acdev->dma_status & ATA_DMA_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dma_xfer(struct arasan_cf_dev *acdev, dma_addr_t src, dma_addr_t dest, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct dma_chan *chan = acdev->dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned long flags = DMA_PREP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tx = chan->device->device_prep_dma_memcpy(chan, dest, src, len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_err(acdev->host->dev, "device_prep_dma_memcpy failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tx->callback = dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) tx->callback_param = acdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) cookie = tx->tx_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(acdev->host->dev, "dma_submit_error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) chan->device->device_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Wait for DMA to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!wait_for_completion_timeout(&acdev->dma_completion, TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dmaengine_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_err(acdev->host->dev, "wait_for_completion_timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int sg_xfer(struct arasan_cf_dev *acdev, struct scatterlist *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dma_addr_t dest = 0, src = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 xfer_cnt, sglen, dma_len, xfer_ctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 write = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) sglen = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) src = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dest = acdev->pbase + EXT_WRITE_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dest = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) src = acdev->pbase + EXT_READ_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * For each sg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * MAX_XFER_COUNT data will be transferred before we get transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * complete interrupt. Between after FIFO_SIZE data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * buffer available interrupt will be generated. At this time we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * fill FIFO again: max FIFO_SIZE data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) while (sglen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) xfer_cnt = min(sglen, MAX_XFER_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) xfer_ctr = readl(acdev->vbase + XFER_CTR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ~XFER_COUNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) writel(xfer_ctr | xfer_cnt | XFER_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) acdev->vbase + XFER_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* continue dma xfers until current sg is completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) while (xfer_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* wait for read to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = wait4buf(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* read/write FIFO in chunk of FIFO_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dma_len = min(xfer_cnt, FIFO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = dma_xfer(acdev, src, dest, dma_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_err(acdev->host->dev, "dma failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) src += dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dest += dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) sglen -= dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) xfer_cnt -= dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* wait for write to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = wait4buf(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) acdev->vbase + XFER_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * This routine uses External DMA controller to read/write data to FIFO of CF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * controller. There are two xfer related interrupt supported by CF controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * - buf_avail: This interrupt is generated as soon as we have buffer of 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * bytes available for reading or empty buffer available for writing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * - xfer_done: This interrupt is generated on transfer of "xfer_size" amount of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * data to/from FIFO. xfer_size is programmed in XFER_CTR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * Max buffer size = FIFO_SIZE = 512 Bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * Max xfer_size = MAX_XFER_COUNT = 256 KB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void data_xfer(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct ata_queued_cmd *qc = acdev->qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* request dma channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* dma_request_channel may sleep, so calling from process context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) acdev->dma_chan = dma_request_chan(acdev->host->dev, "data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (IS_ERR(acdev->dma_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_err(acdev->host->dev, "Unable to get dma_chan\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) acdev->dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto chan_request_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) for_each_sg(qc->sg, sg, qc->n_elem, temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ret = sg_xfer(acdev, sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dma_release_channel(acdev->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) acdev->dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* data xferred successfully */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) status = ioread8(qc->ap->ioaddr.altstatus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (status & (ATA_BUSY | ATA_DRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ata_sff_queue_delayed_work(&acdev->dwork, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto sff_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) cf_dumpregs(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) chan_request_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* error when transferring data to/from memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) qc->err_mask |= AC_ERR_HOST_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) qc->ap->hsm_task_state = HSM_ST_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) cf_ctrl_reset(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) sff_intr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dma_complete(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void delayed_finish(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dwork.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct ata_queued_cmd *qc = acdev->qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) status = ioread8(qc->ap->ioaddr.altstatus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (status & (ATA_BUSY | ATA_DRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ata_sff_queue_delayed_work(&acdev->dwork, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dma_complete(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static irqreturn_t arasan_cf_interrupt(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct arasan_cf_dev *acdev = ((struct ata_host *)dev)->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u32 irqsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) irqsts = readl(acdev->vbase + GIRQ_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!(irqsts & GIRQ_CF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) irqsts = readl(acdev->vbase + IRQ_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) writel(irqsts, acdev->vbase + IRQ_STS); /* clear irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) writel(GIRQ_CF, acdev->vbase + GIRQ_STS); /* clear girqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* handle only relevant interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) irqsts &= ~IGNORED_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (irqsts & CARD_DETECT_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) cf_card_detect(acdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (irqsts & PIO_XFER_ERR_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) acdev->dma_status = ATA_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) acdev->vbase + XFER_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) complete(&acdev->cf_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_err(acdev->host->dev, "pio xfer err irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (irqsts & BUF_AVAIL_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) complete(&acdev->cf_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (irqsts & XFER_DONE_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct ata_queued_cmd *qc = acdev->qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Send Complete only for write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (qc->tf.flags & ATA_TFLAG_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) complete(&acdev->cf_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void arasan_cf_freeze(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct arasan_cf_dev *acdev = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* stop transfer and reset controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) acdev->vbase + XFER_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) cf_ctrl_reset(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) acdev->dma_status = ATA_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ata_sff_dma_pause(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ata_sff_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static void arasan_cf_error_handler(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct arasan_cf_dev *acdev = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * DMA transfers using an external DMA controller may be scheduled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * Abort them before handling error. Refer data_xfer() for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) cancel_work_sync(&acdev->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) cancel_delayed_work_sync(&acdev->dwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return ata_sff_error_handler(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void arasan_cf_dma_start(struct arasan_cf_dev *acdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct ata_queued_cmd *qc = acdev->qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct ata_taskfile *tf = &qc->tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 xfer_ctr = readl(acdev->vbase + XFER_CTR) & ~XFER_DIR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 write = tf->flags & ATA_TFLAG_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) xfer_ctr |= write ? XFER_WRITE : XFER_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) writel(xfer_ctr, acdev->vbase + XFER_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ap->ops->sff_exec_command(ap, tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ata_sff_queue_work(&acdev->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static unsigned int arasan_cf_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct arasan_cf_dev *acdev = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* defer PIO handling to sff_qc_issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (!ata_is_dma(qc->tf.protocol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ata_sff_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* select the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ata_sff_dev_select(ap, qc->dev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* start the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) switch (qc->tf.protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case ATA_PROT_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ap->ops->sff_tf_load(ap, &qc->tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) acdev->dma_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) acdev->qc = qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) arasan_cf_dma_start(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ap->hsm_task_state = HSM_ST_LAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return AC_ERR_SYSTEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static void arasan_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct arasan_cf_dev *acdev = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u8 pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* Arasan ctrl supports Mode0 -> Mode6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (pio > 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(ap->dev, "Unknown PIO mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) val = readl(acdev->vbase + OP_MODE) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ~(ULTRA_DMA_ENB | MULTI_WORD_DMA_ENB | DRQ_BLOCK_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) writel(val, acdev->vbase + OP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) val |= pio << TRUEIDE_PIO_TIMING_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) writel(val, acdev->vbase + TM_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static void arasan_cf_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct arasan_cf_dev *acdev = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u32 opmode, tmcfg, dma_mode = adev->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) spin_lock_irqsave(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) opmode = readl(acdev->vbase + OP_MODE) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ~(MULTI_WORD_DMA_ENB | ULTRA_DMA_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) tmcfg = readl(acdev->vbase + TM_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if ((dma_mode >= XFER_UDMA_0) && (dma_mode <= XFER_UDMA_6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) opmode |= ULTRA_DMA_ENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) tmcfg &= ~ULTRA_DMA_TIMING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) tmcfg |= (dma_mode - XFER_UDMA_0) << ULTRA_DMA_TIMING_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) } else if ((dma_mode >= XFER_MW_DMA_0) && (dma_mode <= XFER_MW_DMA_4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) opmode |= MULTI_WORD_DMA_ENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) tmcfg &= ~TRUEIDE_MWORD_DMA_TIMING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) tmcfg |= (dma_mode - XFER_MW_DMA_0) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) TRUEIDE_MWORD_DMA_TIMING_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_err(ap->dev, "Unknown DMA mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) writel(opmode, acdev->vbase + OP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) writel(tmcfg, acdev->vbase + TM_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) spin_unlock_irqrestore(&acdev->host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct ata_port_operations arasan_cf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .inherits = &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .freeze = arasan_cf_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .error_handler = arasan_cf_error_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .qc_issue = arasan_cf_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .set_piomode = arasan_cf_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .set_dmamode = arasan_cf_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int arasan_cf_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct arasan_cf_dev *acdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct arasan_cf_pdata *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u32 quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) irq_handler_t irq_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) DRIVER_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_warn(&pdev->dev, "Failed to get memory region resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) acdev = devm_kzalloc(&pdev->dev, sizeof(*acdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!acdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) quirk = pdata->quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) quirk = CF_BROKEN_UDMA; /* as it is on spear1340 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * If there's an error getting IRQ (or we do get IRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * support only PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) acdev->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) irq_handler = arasan_cf_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) } else if (ret == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) acdev->pbase = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) acdev->vbase = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (!acdev->vbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_warn(&pdev->dev, "ioremap fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) acdev->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (IS_ERR(acdev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_warn(&pdev->dev, "Clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return PTR_ERR(acdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* allocate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) host = ata_host_alloc(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_warn(&pdev->dev, "alloc host fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) host->private_data = acdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) acdev->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ap->ops = &arasan_cf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ap->pio_mask = ATA_PIO6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ap->mwdma_mask = ATA_MWDMA4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ap->udma_mask = ATA_UDMA6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) init_completion(&acdev->cf_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) init_completion(&acdev->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) INIT_WORK(&acdev->work, data_xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) INIT_DELAYED_WORK(&acdev->dwork, delayed_finish);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dma_cap_set(DMA_MEMCPY, acdev->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* Handle platform specific quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (quirk & CF_BROKEN_PIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ap->ops->set_piomode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ap->pio_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (quirk & CF_BROKEN_MWDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ap->mwdma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (quirk & CF_BROKEN_UDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ap->udma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ap->ioaddr.cmd_addr = acdev->vbase + ATA_DATA_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ap->ioaddr.data_addr = acdev->vbase + ATA_DATA_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ap->ioaddr.error_addr = acdev->vbase + ATA_ERR_FTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ap->ioaddr.feature_addr = acdev->vbase + ATA_ERR_FTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ap->ioaddr.nsect_addr = acdev->vbase + ATA_SC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ap->ioaddr.lbal_addr = acdev->vbase + ATA_SN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ap->ioaddr.lbam_addr = acdev->vbase + ATA_CL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ap->ioaddr.lbah_addr = acdev->vbase + ATA_CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ap->ioaddr.device_addr = acdev->vbase + ATA_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ap->ioaddr.status_addr = acdev->vbase + ATA_STS_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ap->ioaddr.command_addr = acdev->vbase + ATA_STS_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ap->ioaddr.altstatus_addr = acdev->vbase + ATA_ASTS_DCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ap->ioaddr.ctl_addr = acdev->vbase + ATA_ASTS_DCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ata_port_desc(ap, "phy_addr %llx virt_addr %p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) (unsigned long long) res->start, acdev->vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = cf_init(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) cf_card_detect(acdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = ata_host_activate(host, acdev->irq, irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) &arasan_cf_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) cf_exit(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int arasan_cf_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct ata_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct arasan_cf_dev *acdev = host->ports[0]->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ata_host_detach(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) cf_exit(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int arasan_cf_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct arasan_cf_dev *acdev = host->ports[0]->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (acdev->dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dmaengine_terminate_all(acdev->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) cf_exit(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return ata_host_suspend(host, PMSG_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int arasan_cf_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct arasan_cf_dev *acdev = host->ports[0]->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) cf_init(acdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static SIMPLE_DEV_PM_OPS(arasan_cf_pm_ops, arasan_cf_suspend, arasan_cf_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const struct of_device_id arasan_cf_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) { .compatible = "arasan,cf-spear1340" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) MODULE_DEVICE_TABLE(of, arasan_cf_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static struct platform_driver arasan_cf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .probe = arasan_cf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .remove = arasan_cf_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .pm = &arasan_cf_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .of_match_table = of_match_ptr(arasan_cf_id_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) module_platform_driver(arasan_cf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) MODULE_DESCRIPTION("Arasan ATA Compact Flash driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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