^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * pata_ali.c - ALI 15x3 PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (C) 2005 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * based in part upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * linux/drivers/ide/pci/alim15x3.c Version 0.17 2003/01/02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1998-2000 Michel Aubry, Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 2002 Alan Cox <alan@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Chipset documentation available under NDA only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * TODO/CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Cannot have ATAPI on both master & slave for rev < c2 (???) but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * otherwise should do atapi DMA (For now for old we do PIO only for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * ATAPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Review Sunblade workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRV_NAME "pata_ali"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRV_VERSION "0.7.8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int ali_atapi_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) module_param_named(atapi_dma, ali_atapi_dma, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_PARM_DESC(atapi_dma, "Enable ATAPI DMA (0=disable, 1=enable)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct pci_dev *ali_isa_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Cable special cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct dmi_system_id cable_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .ident = "HP Pavilion N5430",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .ident = "Toshiba Satellite S1800-814",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int ali_cable_override(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Fujitsu P2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (pdev->subsystem_vendor == 0x10CF && pdev->subsystem_device == 0x10AF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Mitac 8317 (Winbook-A) and relatives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (pdev->subsystem_vendor == 0x1071 && pdev->subsystem_device == 0x8317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Systems by DMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (dmi_check_system(cable_dmi_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * ali_c2_cable_detect - cable detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Perform cable detection for C2 and later revisions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int ali_c2_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 ata66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Certain laptops use short but suitable cables and don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) implement the detect logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (ali_cable_override(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return ATA_CBL_PATA40_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Host view cable detect 0x4A bit 0 primary bit 1 secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) Bit set for 40 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pci_read_config_byte(pdev, 0x4A, &ata66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ata66 & (1 << ap->port_no))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * ali_20_filter - filter for earlier ALI DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @ap: ALi ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @adev: attached device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Ensure that we do not do DMA on CD devices. We may be able to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * fix that later on. Also ensure we do not do UDMA on WDC drives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static unsigned long ali_20_filter(struct ata_device *adev, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) char model_num[ATA_ID_PROD_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* No DMA on anything but a disk for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (adev->class != ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (strstr(model_num, "WDC"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return mask &= ~ATA_MASK_UDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * ali_fifo_control - FIFO manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @ap: ALi channel to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @adev: device for FIFO control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @on: 0 for off 1 for on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Enable or disable the FIFO on a given device. Because of the way the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * ALi FIFO works it provides a boost on ATA disk but can be confused by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * ATAPI and we must therefore manage it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void ali_fifo_control(struct ata_port *ap, struct ata_device *adev, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int pio_fifo = 0x54 + ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int shift = 4 * adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* ATA - FIFO on set nibble to 0x05, ATAPI - FIFO off, set nibble to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0x00. Not all the docs agree but the behaviour we now use is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) one stated in the BIOS Programming Guide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pci_read_config_byte(pdev, pio_fifo, &fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) fifo &= ~(0x0F << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) fifo |= (on << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pci_write_config_byte(pdev, pio_fifo, fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * ali_program_modes - load mode registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @ap: ALi channel to load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @adev: Device the timing is for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @t: timing data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @ultra: UDMA timing or zero for off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Loads the timing registers for cmd/data and disable UDMA if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * ultra is zero. If ultra is set then load and enable the UDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * timing but do not touch the command/data timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void ali_program_modes(struct ata_port *ap, struct ata_device *adev, struct ata_timing *t, u8 ultra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int cas = 0x58 + 4 * ap->port_no; /* Command timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int cbt = 0x59 + 4 * ap->port_no; /* Command timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int drwt = 0x5A + 4 * ap->port_no + adev->devno; /* R/W timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int udmat = 0x56 + ap->port_no; /* UDMA timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int shift = 4 * adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 udma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (t != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) t->setup = clamp_val(t->setup, 1, 8) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) t->act8b = clamp_val(t->act8b, 1, 8) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) t->rec8b = clamp_val(t->rec8b, 1, 16) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) t->active = clamp_val(t->active, 1, 8) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) t->recover = clamp_val(t->recover, 1, 16) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pci_write_config_byte(pdev, cas, t->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pci_write_config_byte(pdev, cbt, (t->act8b << 4) | t->rec8b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pci_write_config_byte(pdev, drwt, (t->active << 4) | t->recover);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Set up the UDMA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pci_read_config_byte(pdev, udmat, &udma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) udma &= ~(0x0F << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) udma |= ultra << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pci_write_config_byte(pdev, udmat, udma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * ali_set_piomode - set initial PIO mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Program the ALi registers for PIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void ali_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned long T = 1000000000 / 33333; /* PCI clock based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ata_timing_compute(adev, adev->pio_mode, &t, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct ata_timing p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (pair->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ata_timing_compute(pair, pair->dma_mode, &p, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* PIO FIFO is only permitted on ATA disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (adev->class != ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ali_fifo_control(ap, adev, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ali_program_modes(ap, adev, &t, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (adev->class == ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ali_fifo_control(ap, adev, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * ali_set_dmamode - set initial DMA mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Program the ALi registers for DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void ali_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static u8 udma_timing[7] = { 0xC, 0xB, 0xA, 0x9, 0x8, 0xF, 0xD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned long T = 1000000000 / 33333; /* PCI clock based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (adev->class == ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ali_fifo_control(ap, adev, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (adev->dma_mode >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ali_program_modes(ap, adev, NULL, udma_timing[adev->dma_mode - XFER_UDMA_0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (adev->dma_mode >= XFER_UDMA_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 reg4b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pci_read_config_byte(pdev, 0x4B, ®4b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) reg4b |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pci_write_config_byte(pdev, 0x4B, reg4b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ata_timing_compute(adev, adev->dma_mode, &t, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct ata_timing p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (pair->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ata_timing_compute(pair, pair->dma_mode, &p, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ali_program_modes(ap, adev, &t, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * ali_warn_atapi_dma - Warn about ATAPI DMA disablement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * @adev: Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Whine about ATAPI DMA disablement if @adev is an ATAPI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Can be used as ->dev_config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void ali_warn_atapi_dma(struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct ata_eh_context *ehc = &adev->link->eh_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int print_info = ehc->i.flags & ATA_EHI_PRINTINFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (print_info && adev->class == ATA_DEV_ATAPI && !ali_atapi_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ata_dev_warn(adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "WARNING: ATAPI DMA disabled for reliability issues. It can be enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ata_dev_warn(adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "WARNING: via pata_ali.atapi_dma modparam or corresponding sysfs node.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * ali_lock_sectors - Keep older devices to 255 sector mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @adev: Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Called during the bus probe for each device that is found. We use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * this call to lock the sector count of the device to 255 or less on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * older ALi controllers. If we didn't do this then large I/O's would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * require LBA48 commands which the older ALi requires are issued by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * slower PIO methods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void ali_lock_sectors(struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) adev->max_sectors = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ali_warn_atapi_dma(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * ali_check_atapi_dma - DMA check for most ALi controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @adev: Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Called to decide whether commands should be sent by DMA or PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int ali_check_atapi_dma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!ali_atapi_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* FIXME: pata_ali can't do ATAPI DMA reliably but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * IDE alim15x3 driver can. I tried lots of things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * but couldn't find what the actual difference was.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * If you got an idea, please write it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * linux-ide@vger.kernel.org and cc htejun@gmail.com.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Disable ATAPI DMA for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* If its not a media command, its not worth it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (atapi_cmd_type(qc->cdb[0]) == ATAPI_MISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void ali_c2_c3_postreset(struct ata_link *link, unsigned int *classes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int port_bit = 4 << link->ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* If our bridge is an ALI 1533 then do the extra work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ali_isa_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Tristate and re-enable the bus signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pci_read_config_byte(ali_isa_bridge, 0x58, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) r &= ~port_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pci_write_config_byte(ali_isa_bridge, 0x58, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) r |= port_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pci_write_config_byte(ali_isa_bridge, 0x58, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ata_sff_postreset(link, classes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct scsi_host_template ali_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Port operations for PIO only ALi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static struct ata_port_operations ali_early_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .inherits = &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .set_piomode = ali_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .sff_data_xfer = ata_sff_data_xfer32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct ata_port_operations ali_dma_base_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .inherits = &ata_bmdma32_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .set_piomode = ali_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .set_dmamode = ali_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Port operations for DMA capable ALi without cable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct ata_port_operations ali_20_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .inherits = &ali_dma_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .mode_filter = ali_20_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .check_atapi_dma = ali_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .dev_config = ali_lock_sectors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Port operations for DMA capable ALi with cable detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct ata_port_operations ali_c2_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .inherits = &ali_dma_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .check_atapi_dma = ali_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .cable_detect = ali_c2_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .dev_config = ali_lock_sectors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .postreset = ali_c2_c3_postreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Port operations for DMA capable ALi with cable detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct ata_port_operations ali_c4_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .inherits = &ali_dma_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .check_atapi_dma = ali_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .cable_detect = ali_c2_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .dev_config = ali_lock_sectors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Port operations for DMA capable ALi with cable detect and LBA48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct ata_port_operations ali_c5_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .inherits = &ali_dma_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .check_atapi_dma = ali_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .dev_config = ali_warn_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .cable_detect = ali_c2_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * ali_init_chipset - chip setup function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * @pdev: PCI device of ATA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Perform the setup on the device that must be done both at boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * and at resume time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static void ali_init_chipset(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct pci_dev *north;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * The chipset revision selects the driver operations and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * mode data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (pdev->revision <= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pci_read_config_byte(pdev, 0x53, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) tmp |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pci_write_config_byte(pdev, 0x53, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pci_read_config_byte(pdev, 0x4a, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pci_write_config_byte(pdev, 0x4a, tmp | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pci_read_config_byte(pdev, 0x4B, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (pdev->revision < 0xC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* 1543-E/F, 1543C-C, 1543C-D, 1543C-E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Clear CD-ROM DMA write bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tmp &= 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Cable and UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (pdev->revision >= 0xc2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) tmp |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pci_write_config_byte(pdev, 0x4B, tmp | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * CD_ROM DMA on (0x53 bit 0). Enable this even if we want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * to use PIO. 0x53 bit 1 (rev 20 only) - enable FIFO control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * via 0x54/55.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pci_read_config_byte(pdev, 0x53, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (pdev->revision >= 0xc7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tmp |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) tmp |= 0x01; /* CD_ROM enable for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pci_write_config_byte(pdev, 0x53, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) north = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PCI_DEVFN(0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (north && north->vendor == PCI_VENDOR_ID_AL && ali_isa_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Configure the ALi bridge logic. For non ALi rely on BIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) Set the south bridge enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pci_read_config_byte(ali_isa_bridge, 0x79, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (pdev->revision == 0xC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) pci_write_config_byte(ali_isa_bridge, 0x79, tmp | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) else if (pdev->revision > 0xC2 && pdev->revision < 0xC5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pci_write_config_byte(ali_isa_bridge, 0x79, tmp | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pci_dev_put(north);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ata_pci_bmdma_clear_simplex(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * ali_init_one - discovery callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * @pdev: PCI device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * @id: PCI table info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * An ALi IDE interface has been discovered. Figure out what revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * and perform configuration work before handing it to the ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct ata_port_info info_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .port_ops = &ali_early_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Revision 0x20 added DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const struct ata_port_info info_20 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ATA_FLAG_IGN_SIMPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .port_ops = &ali_20_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Revision 0x20 with support logic added UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct ata_port_info info_20_udma = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ATA_FLAG_IGN_SIMPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .port_ops = &ali_20_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Revision 0xC2 adds UDMA66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct ata_port_info info_c2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ATA_FLAG_IGN_SIMPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .port_ops = &ali_c2_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Revision 0xC3 is UDMA66 for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct ata_port_info info_c3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ATA_FLAG_IGN_SIMPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .port_ops = &ali_c2_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Revision 0xC4 is UDMA100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct ata_port_info info_c4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_LBA48 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ATA_FLAG_IGN_SIMPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .port_ops = &ali_c4_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Revision 0xC5 is UDMA133 with LBA48 DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const struct ata_port_info info_c5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_IGN_SIMPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .port_ops = &ali_c5_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) const struct ata_port_info *ppi[] = { NULL, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * The chipset revision selects the driver operations and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * mode data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (pdev->revision < 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ppi[0] = &info_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) } else if (pdev->revision < 0xC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ppi[0] = &info_20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) } else if (pdev->revision == 0xC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ppi[0] = &info_c2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } else if (pdev->revision == 0xC3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ppi[0] = &info_c3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) } else if (pdev->revision == 0xC4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ppi[0] = &info_c4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ppi[0] = &info_c5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ali_init_chipset(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ali_isa_bridge && pdev->revision >= 0x20 && pdev->revision < 0xC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Are we paired with a UDMA capable chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pci_read_config_byte(ali_isa_bridge, 0x5E, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if ((tmp & 0x1E) == 0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ppi[0] = &info_20_udma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!ppi[0]->mwdma_mask && !ppi[0]->udma_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ata_pci_sff_init_one(pdev, ppi, &ali_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ata_pci_bmdma_init_one(pdev, ppi, &ali_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int ali_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ali_init_chipset(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const struct pci_device_id ali[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static struct pci_driver ali_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .id_table = ali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .probe = ali_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .resume = ali_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int __init ali_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = pci_register_driver(&ali_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pci_dev_put(ali_isa_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static void __exit ali_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) pci_unregister_driver(&ali_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) pci_dev_put(ali_isa_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MODULE_DESCRIPTION("low-level driver for ALi PATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) MODULE_DEVICE_TABLE(pci, ali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) module_init(ali_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) module_exit(ali_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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