^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Helper library for PATA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2003-2004 Jeff Garzik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This mode timing computation functionality is ported over from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * These were taken from ATA/ATAPI-6 standard, rev 0a, except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * for UDMA6, which is currently supported only by Maxtor drives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * For PIO 5/6 MWDMA 3/4 see the CFA specification 3.0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct ata_timing ata_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 0, 960, 0 }, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 0, 600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 0, 383, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 0, 240, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 0, 180, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 0, 120, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 0, 100, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 0, 80, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 50, 960, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 30, 480, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 20, 240, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 20, 480, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 5, 150, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 5, 120, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 5, 100, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 5, 80, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 0, 150 }, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 0, 120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 0, 80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 0, 60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 0, 45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 0, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 0, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 0, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 0xFF }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ENOUGH(v, unit) (((v)-1)/(unit)+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EZ(v, unit) ((v)?ENOUGH(((v) * 1000), unit):0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void ata_timing_quantize(const struct ata_timing *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct ata_timing *q, int T, int UT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) q->setup = EZ(t->setup, T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) q->act8b = EZ(t->act8b, T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) q->rec8b = EZ(t->rec8b, T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) q->cyc8b = EZ(t->cyc8b, T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) q->active = EZ(t->active, T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) q->recover = EZ(t->recover, T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) q->dmack_hold = EZ(t->dmack_hold, T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) q->cycle = EZ(t->cycle, T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) q->udma = EZ(t->udma, UT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct ata_timing *m, unsigned int what)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (what & ATA_TIMING_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) m->setup = max(a->setup, b->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (what & ATA_TIMING_ACT8B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) m->act8b = max(a->act8b, b->act8b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (what & ATA_TIMING_REC8B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) m->rec8b = max(a->rec8b, b->rec8b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (what & ATA_TIMING_CYC8B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) m->cyc8b = max(a->cyc8b, b->cyc8b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (what & ATA_TIMING_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) m->active = max(a->active, b->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (what & ATA_TIMING_RECOVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) m->recover = max(a->recover, b->recover);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (what & ATA_TIMING_DMACK_HOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) m->dmack_hold = max(a->dmack_hold, b->dmack_hold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (what & ATA_TIMING_CYCLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) m->cycle = max(a->cycle, b->cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (what & ATA_TIMING_UDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) m->udma = max(a->udma, b->udma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) EXPORT_SYMBOL_GPL(ata_timing_merge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const struct ata_timing *ata_timing_find_mode(u8 xfer_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const struct ata_timing *t = ata_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) while (xfer_mode > t->mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) t++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (xfer_mode == t->mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) WARN_ONCE(true, "%s: unable to find timing for xfer_mode 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __func__, xfer_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) EXPORT_SYMBOL_GPL(ata_timing_find_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int ata_timing_compute(struct ata_device *adev, unsigned short speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct ata_timing *t, int T, int UT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const u16 *id = adev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const struct ata_timing *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct ata_timing p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Find the mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) s = ata_timing_find_mode(speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) memcpy(t, s, sizeof(*s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * If the drive is an EIDE drive, it can tell us it needs extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * PIO/MW_DMA cycle timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) memset(&p, 0, sizeof(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (speed <= XFER_PIO_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) else if ((speed <= XFER_PIO_4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) p.cycle = id[ATA_ID_EIDE_DMA_MIN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Convert the timing to bus clock counts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ata_timing_quantize(t, t, T, UT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * S.M.A.R.T * and some other commands. We have to ensure that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * DMA cycle timing is slower/equal than the fastest PIO timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (speed > XFER_PIO_6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Lengthen active & recovery time so that cycle time is correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (t->act8b + t->rec8b < t->cyc8b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) t->rec8b = t->cyc8b - t->act8b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (t->active + t->recover < t->cycle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) t->active += (t->cycle - (t->active + t->recover)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) t->recover = t->cycle - t->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * In a few cases quantisation may produce enough errors to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * leave t->cycle too low for the sum of active and recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * if so we must correct this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (t->active + t->recover > t->cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) t->cycle = t->active + t->recover;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) EXPORT_SYMBOL_GPL(ata_timing_compute);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags