^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * libahci.c - Common AHCI SATA low-level routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintained by: Tejun Heo <tj@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Please ALWAYS copy linux-ide@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * on emails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2004-2005 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * AHCI hardware documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/nospec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "libata.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int ahci_skip_host_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int ahci_ignore_sss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) EXPORT_SYMBOL_GPL(ahci_ignore_sss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned hints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ssize_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int ahci_port_start(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void ahci_port_stop(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void ahci_freeze(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void ahci_thaw(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void ahci_enable_fbs(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void ahci_disable_fbs(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void ahci_pmp_attach(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void ahci_pmp_detach(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int ahci_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int ahci_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void ahci_postreset(struct ata_link *link, unsigned int *class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void ahci_dev_config(struct ata_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static ssize_t ahci_activity_store(struct ata_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum sw_activity val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void ahci_init_sw_activity(struct ata_link *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static ssize_t ahci_show_host_caps(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct device_attribute *attr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static ssize_t ahci_show_host_cap2(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct device_attribute *attr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static ssize_t ahci_show_host_version(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct device_attribute *attr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static ssize_t ahci_show_port_cmd(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct device_attribute *attr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static ssize_t ahci_read_em_buffer(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct device_attribute *attr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static ssize_t ahci_store_em_buffer(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const char *buf, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static ssize_t ahci_show_em_supported(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device_attribute *attr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ahci_read_em_buffer, ahci_store_em_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct device_attribute *ahci_shost_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) &dev_attr_link_power_management_policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) &dev_attr_em_message_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) &dev_attr_em_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) &dev_attr_ahci_host_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) &dev_attr_ahci_host_cap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) &dev_attr_ahci_host_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) &dev_attr_ahci_port_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) &dev_attr_em_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) &dev_attr_em_message_supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) EXPORT_SYMBOL_GPL(ahci_shost_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct device_attribute *ahci_sdev_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) &dev_attr_sw_activity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) &dev_attr_unload_heads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) &dev_attr_ncq_prio_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct ata_port_operations ahci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .inherits = &sata_pmp_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .qc_defer = ahci_pmp_qc_defer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .qc_prep = ahci_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .qc_issue = ahci_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .qc_fill_rtf = ahci_qc_fill_rtf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .freeze = ahci_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .thaw = ahci_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .softreset = ahci_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .hardreset = ahci_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .postreset = ahci_postreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .pmp_softreset = ahci_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .error_handler = ahci_error_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .post_internal_cmd = ahci_post_internal_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .dev_config = ahci_dev_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .scr_read = ahci_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .scr_write = ahci_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .pmp_attach = ahci_pmp_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .pmp_detach = ahci_pmp_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .set_lpm = ahci_set_lpm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .em_show = ahci_led_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .em_store = ahci_led_store,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .sw_activity_show = ahci_activity_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .sw_activity_store = ahci_activity_store,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .transmit_led_message = ahci_transmit_led_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .port_suspend = ahci_port_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .port_resume = ahci_port_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .port_start = ahci_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .port_stop = ahci_port_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) EXPORT_SYMBOL_GPL(ahci_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct ata_port_operations ahci_pmp_retry_srst_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .softreset = ahci_pmp_retry_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static bool ahci_em_messages __read_mostly = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) module_param(ahci_em_messages, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* add other LED protocol types when they become supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MODULE_PARM_DESC(ahci_em_messages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "AHCI Enclosure Management Message control (0 = off, 1 = on)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* device sleep idle timeout in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int devslp_idle_timeout __read_mostly = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) module_param(devslp_idle_timeout, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void ahci_enable_ahci(void __iomem *mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* turn on AHCI_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) tmp = readl(mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (tmp & HOST_AHCI_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Some controllers need AHCI_EN to be written multiple times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Try a few times before giving up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tmp |= HOST_AHCI_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) writel(tmp, mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (tmp & HOST_AHCI_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * ahci_rpm_get_port - Make sure the port is powered on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @ap: Port to power on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Whenever there is need to access the AHCI host registers outside of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * normal execution paths, call this function to make sure the host is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * actually powered on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int ahci_rpm_get_port(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return pm_runtime_get_sync(ap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @ap: Port to power down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * if it has no more active users.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void ahci_rpm_put_port(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pm_runtime_put(ap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static ssize_t ahci_show_host_caps(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct Scsi_Host *shost = class_to_shost(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct ata_port *ap = ata_shost_to_port(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return sprintf(buf, "%x\n", hpriv->cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static ssize_t ahci_show_host_cap2(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct Scsi_Host *shost = class_to_shost(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct ata_port *ap = ata_shost_to_port(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return sprintf(buf, "%x\n", hpriv->cap2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static ssize_t ahci_show_host_version(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct Scsi_Host *shost = class_to_shost(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct ata_port *ap = ata_shost_to_port(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return sprintf(buf, "%x\n", hpriv->version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static ssize_t ahci_show_port_cmd(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct Scsi_Host *shost = class_to_shost(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct ata_port *ap = ata_shost_to_port(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ahci_rpm_get_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static ssize_t ahci_read_em_buffer(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct Scsi_Host *shost = class_to_shost(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct ata_port *ap = ata_shost_to_port(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void __iomem *em_mmio = mmio + hpriv->em_loc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 em_ctl, msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) size_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ahci_rpm_get_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_lock_irqsave(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) em_ctl = readl(mmio + HOST_EM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spin_unlock_irqrestore(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!(em_ctl & EM_CTL_MR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_unlock_irqrestore(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!(em_ctl & EM_CTL_SMB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) em_mmio += hpriv->em_buf_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) count = hpriv->em_buf_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* the count should not be larger than PAGE_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (count > PAGE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (printk_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ata_port_warn(ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "EM read buffer size too large: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "buffer size %u, page size %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) hpriv->em_buf_sz, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) count = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) for (i = 0; i < count; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) msg = readl(em_mmio + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) buf[i] = msg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) buf[i + 1] = (msg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) buf[i + 2] = (msg >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) buf[i + 3] = (msg >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) spin_unlock_irqrestore(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static ssize_t ahci_store_em_buffer(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) const char *buf, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct Scsi_Host *shost = class_to_shost(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct ata_port *ap = ata_shost_to_port(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void __iomem *em_mmio = mmio + hpriv->em_loc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) const unsigned char *msg_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 em_ctl, msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* check size validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!(ap->flags & ATA_FLAG_EM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) size % 4 || size > hpriv->em_buf_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ahci_rpm_get_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) spin_lock_irqsave(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) em_ctl = readl(mmio + HOST_EM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (em_ctl & EM_CTL_TM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) spin_unlock_irqrestore(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (i = 0; i < size; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) msg = msg_buf[i] | msg_buf[i + 1] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) writel(msg, em_mmio + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) spin_unlock_irqrestore(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static ssize_t ahci_show_em_supported(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct Scsi_Host *shost = class_to_shost(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct ata_port *ap = ata_shost_to_port(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 em_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ahci_rpm_get_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) em_ctl = readl(mmio + HOST_EM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return sprintf(buf, "%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) em_ctl & EM_CTL_LED ? "led " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) em_ctl & EM_CTL_SES ? "ses-2 " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * ahci_save_initial_config - Save and fixup initial config values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * @dev: target AHCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * @hpriv: host private area to store config values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Some registers containing configuration info might be setup by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * BIOS and might be cleared on reset. This function saves the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * initial values of those registers into @hpriv such that they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * can be restored after controller reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * If inconsistent, config values are fixed up by this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * If it is not set already this function sets hpriv->start_engine to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * ahci_start_engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * None.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 cap, cap2, vers, port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* make sure AHCI mode is enabled before accessing CAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ahci_enable_ahci(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Values prefixed with saved_ are written back to host after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * reset. Values without are used for driver operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* CAP2 register is only defined for AHCI 1.2 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) vers = readl(mmio + HOST_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if ((vers >> 16) > 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) hpriv->saved_cap2 = cap2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* some chips have errata preventing 64bit use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) cap &= ~HOST_CAP_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cap &= ~HOST_CAP_NCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) cap |= HOST_CAP_NCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) cap &= ~HOST_CAP_PMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "controller can't do SNTF, turning off CAP_SNTF\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) cap &= ~HOST_CAP_SNTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "controller can't do DEVSLP, turning off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) cap2 &= ~HOST_CAP2_SDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cap2 &= ~HOST_CAP2_SADM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) cap |= HOST_CAP_FBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) cap &= ~HOST_CAP_FBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) cap |= HOST_CAP_ALPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cap &= ~HOST_CAP_SXS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) port_map, hpriv->force_port_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) port_map = hpriv->force_port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) hpriv->saved_port_map = port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (hpriv->mask_port_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) port_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) port_map & hpriv->mask_port_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) port_map &= hpriv->mask_port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* cross check port_map and cap.n_ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (port_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int map_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) for (i = 0; i < AHCI_MAX_PORTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (port_map & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) map_ports++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* If PI has more ports than n_ports, whine, clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * port_map and let it be generated from n_ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (map_ports > ahci_nr_ports(cap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) port_map, ahci_nr_ports(cap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) port_map = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!port_map && vers < 0x10300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) port_map = (1 << ahci_nr_ports(cap)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* write the fixed up value to the PI register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hpriv->saved_port_map = port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* record values to use during operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) hpriv->cap = cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hpriv->cap2 = cap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) hpriv->version = readl(mmio + HOST_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) hpriv->port_map = port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!hpriv->start_engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) hpriv->start_engine = ahci_start_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!hpriv->stop_engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) hpriv->stop_engine = ahci_stop_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!hpriv->irq_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hpriv->irq_handler = ahci_single_level_irq_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) EXPORT_SYMBOL_GPL(ahci_save_initial_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * ahci_restore_initial_config - Restore initial config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * @host: target ATA host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * Restore initial config stored by ahci_save_initial_config().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * None.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static void ahci_restore_initial_config(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) writel(hpriv->saved_cap, mmio + HOST_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (hpriv->saved_cap2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) writel(hpriv->saved_cap2, mmio + HOST_CAP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const int offset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) [SCR_STATUS] = PORT_SCR_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) [SCR_CONTROL] = PORT_SCR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) [SCR_ERROR] = PORT_SCR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) [SCR_ACTIVE] = PORT_SCR_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) [SCR_NOTIFICATION] = PORT_SCR_NTF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (sc_reg < ARRAY_SIZE(offset) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return offset[sc_reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) void __iomem *port_mmio = ahci_port_base(link->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int offset = ahci_scr_offset(link->ap, sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) *val = readl(port_mmio + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) void __iomem *port_mmio = ahci_port_base(link->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int offset = ahci_scr_offset(link->ap, sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) writel(val, port_mmio + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) void ahci_start_engine(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) tmp = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) tmp |= PORT_CMD_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) writel(tmp, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) readl(port_mmio + PORT_CMD); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) EXPORT_SYMBOL_GPL(ahci_start_engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int ahci_stop_engine(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * On some controllers, stopping a port's DMA engine while the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * is in ALPM state (partial or slumber) results in failures on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * subsequent DMA engine starts. For those controllers, put the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * port back in active state before stopping its DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) tmp = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* check if the HBA is idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Don't try to issue commands but return with ENODEV if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * AHCI controller not available anymore (e.g. due to PCIe hot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * unplugging). Otherwise a 500ms delay for each port is added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (tmp == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dev_err(ap->host->dev, "AHCI controller unavailable!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* setting HBA to idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) tmp &= ~PORT_CMD_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) writel(tmp, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* wait for engine to stop. This could be as long as 500 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (tmp & PORT_CMD_LIST_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) EXPORT_SYMBOL_GPL(ahci_stop_engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) void ahci_start_fis_rx(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* set FIS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (hpriv->cap & HOST_CAP_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) writel((pp->cmd_slot_dma >> 16) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) port_mmio + PORT_LST_ADDR_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (hpriv->cap & HOST_CAP_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) writel((pp->rx_fis_dma >> 16) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) port_mmio + PORT_FIS_ADDR_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* enable FIS reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) tmp = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) tmp |= PORT_CMD_FIS_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) writel(tmp, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int ahci_stop_fis_rx(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* disable FIS reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) tmp = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) tmp &= ~PORT_CMD_FIS_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) writel(tmp, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* wait for completion, spec says 500ms, give it 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PORT_CMD_FIS_ON, 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (tmp & PORT_CMD_FIS_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static void ahci_power_up(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* spin up device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (hpriv->cap & HOST_CAP_SSS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) cmd |= PORT_CMD_SPIN_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) writel(cmd, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* wake up link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unsigned int hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (policy != ATA_LPM_MAX_POWER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* wakeup flag only applies to the max power policy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) hints &= ~ATA_LPM_WAKE_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Disable interrupts on Phy Ready. This keeps us from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * getting woken up due to spurious phy ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pp->intr_mask &= ~PORT_IRQ_PHYRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) sata_link_scr_lpm(link, policy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (hpriv->cap & HOST_CAP_ALPM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 cmd = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (!(hints & ATA_LPM_WAKE_ONLY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) cmd |= PORT_CMD_ICC_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) writel(cmd, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* wait 10ms to be sure we've come out of LPM state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ata_msleep(ap, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (hints & ATA_LPM_WAKE_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) cmd |= PORT_CMD_ALPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (policy == ATA_LPM_MIN_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) cmd |= PORT_CMD_ASP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) cmd &= ~PORT_CMD_ASP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* write out new cmd value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) writel(cmd, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* set aggressive device sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if ((hpriv->cap2 & HOST_CAP2_SDS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) (hpriv->cap2 & HOST_CAP2_SADM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) (link->device->flags & ATA_DFLAG_DEVSLP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (policy == ATA_LPM_MIN_POWER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ahci_set_aggressive_devslp(ap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ahci_set_aggressive_devslp(ap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (policy == ATA_LPM_MAX_POWER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) sata_link_scr_lpm(link, policy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* turn PHYRDY IRQ back on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pp->intr_mask |= PORT_IRQ_PHYRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static void ahci_power_down(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 cmd, scontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (!(hpriv->cap & HOST_CAP_SSS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* put device into listen mode, first set PxSCTL.DET to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) scontrol = readl(port_mmio + PORT_SCR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) scontrol &= ~0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) writel(scontrol, port_mmio + PORT_SCR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* then set PxCMD.SUD to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) cmd &= ~PORT_CMD_SPIN_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) writel(cmd, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static void ahci_start_port(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct ata_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct ahci_em_priv *emp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ssize_t rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* enable FIS reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ahci_start_fis_rx(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* enable DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* turn on LEDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (ap->flags & ATA_FLAG_EM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ata_for_each_link(link, ap, EDGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) emp = &pp->em_priv[link->pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* EM Transmit bit maybe busy during init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) for (i = 0; i < EM_MAX_RETRY; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) rc = ap->ops->transmit_led_message(ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) emp->led_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * If busy, give a breather but do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * release EH ownership by using msleep()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * instead of ata_msleep(). EM Transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * bit is busy for the whole host and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * releasing ownership will cause other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * ports to fail the same way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (rc == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (ap->flags & ATA_FLAG_SW_ACTIVITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ata_for_each_link(link, ap, EDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ahci_init_sw_activity(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* disable DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) rc = hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) *emsg = "failed to stop engine";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* disable FIS reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) rc = ahci_stop_fis_rx(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) *emsg = "failed stop FIS RX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int ahci_reset_controller(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* we must be in AHCI mode, before using anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * AHCI-specific, such as HOST_RESET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ahci_enable_ahci(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* global controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!ahci_skip_host_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) tmp = readl(mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if ((tmp & HOST_RESET) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) writel(tmp | HOST_RESET, mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) readl(mmio + HOST_CTL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * to perform host reset, OS should set HOST_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * and poll until this bit is read to be "0".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * reset must complete within 1 second, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * the hardware should be considered fried.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) HOST_RESET, 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (tmp & HOST_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dev_err(host->dev, "controller reset failed (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* turn on AHCI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ahci_enable_ahci(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Some registers might be cleared on reset. Restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * initial values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ahci_restore_initial_config(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_info(host->dev, "skipping global host reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) EXPORT_SYMBOL_GPL(ahci_reset_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static void ahci_sw_activity(struct ata_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) emp->activity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!timer_pending(&emp->timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static void ahci_sw_activity_blink(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct ahci_em_priv *emp = from_timer(emp, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct ata_link *link = emp->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned long led_message = emp->led_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) u32 activity_led_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) led_message &= EM_MSG_LED_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) led_message |= ap->port_no | (link->pmp << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* check to see if we've had activity. If so,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * toggle state of LED and reset timer. If not,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * turn LED to desired idle state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) spin_lock_irqsave(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (emp->saved_activity != emp->activity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) emp->saved_activity = emp->activity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* get the current LED state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (activity_led_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) activity_led_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) activity_led_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* clear old state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* toggle state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) led_message |= (activity_led_state << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* switch to idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (emp->blink_policy == BLINK_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) led_message |= (1 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) spin_unlock_irqrestore(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ap->ops->transmit_led_message(ap, led_message, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static void ahci_init_sw_activity(struct ata_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* init activity stats, setup timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) emp->saved_activity = emp->activity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) emp->link = link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* check our blink policy and set flag for link if it's enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (emp->blink_policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) link->flags |= ATA_LFLAG_SW_ACTIVITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int ahci_reset_em(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) u32 em_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) em_ctl = readl(mmio + HOST_EM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) EXPORT_SYMBOL_GPL(ahci_reset_em);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ssize_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u32 em_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u32 message[] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) int pmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct ahci_em_priv *emp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* get the slot number from the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (pmp < EM_MAX_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) emp = &pp->em_priv[pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ahci_rpm_get_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) spin_lock_irqsave(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * if we are still busy transmitting a previous message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * do not allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) em_ctl = readl(mmio + HOST_EM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (em_ctl & EM_CTL_TM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) spin_unlock_irqrestore(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * create message header - this is all zero except for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * the message size, which is 4 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) message[0] |= (4 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* ignore 0:4 of byte zero, fill in port info yourself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* write message to EM_LOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) writel(message[0], mmio + hpriv->em_loc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) writel(message[1], mmio + hpriv->em_loc+4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * tell hardware to transmit the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* save off new led state for port/slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) emp->led_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) spin_unlock_irqrestore(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct ata_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct ahci_em_priv *emp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ata_for_each_link(link, ap, EDGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) emp = &pp->em_priv[link->pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) rc += sprintf(buf, "%lx\n", emp->led_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) unsigned int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) int pmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct ahci_em_priv *emp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (kstrtouint(buf, 0, &state) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* get the slot number from the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (pmp < EM_MAX_SLOTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) emp = &pp->em_priv[pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* mask off the activity bits if we are in sw_activity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * mode, user should turn off sw_activity before setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * activity led through em_message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (emp->blink_policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) state &= ~EM_MSG_LED_VALUE_ACTIVITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return ap->ops->transmit_led_message(ap, state, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct ata_link *link = dev->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) u32 port_led_state = emp->led_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* save the desired Activity LED behavior */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (val == OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* clear LFLAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* set the LED to OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) port_led_state &= EM_MSG_LED_VALUE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) port_led_state |= (ap->port_no | (link->pmp << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ap->ops->transmit_led_message(ap, port_led_state, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) link->flags |= ATA_LFLAG_SW_ACTIVITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (val == BLINK_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* set LED to ON for idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) port_led_state &= EM_MSG_LED_VALUE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) port_led_state |= (ap->port_no | (link->pmp << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ap->ops->transmit_led_message(ap, port_led_state, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) emp->blink_policy = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct ata_link *link = dev->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* display the saved value of activity behavior for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * disk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return sprintf(buf, "%d\n", emp->blink_policy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static void ahci_port_init(struct device *dev, struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) int port_no, void __iomem *mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) void __iomem *port_mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) const char *emsg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* make sure port is not active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) rc = ahci_deinit_port(ap, &emsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_warn(dev, "%s (%d)\n", emsg, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* clear SError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) tmp = readl(port_mmio + PORT_SCR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) writel(tmp, port_mmio + PORT_SCR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* clear port IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) tmp = readl(port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) writel(tmp, port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) writel(1 << port_no, mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* mark esata ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) tmp = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ap->pflags |= ATA_PFLAG_EXTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) void ahci_init_controller(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) void __iomem *port_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (ata_port_is_dummy(ap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ahci_port_init(host->dev, ap, i, mmio, port_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) tmp = readl(mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) VPRINTK("HOST_CTL 0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) tmp = readl(mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) VPRINTK("HOST_CTL 0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) EXPORT_SYMBOL_GPL(ahci_init_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static void ahci_dev_config(struct ata_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (hpriv->flags & AHCI_HFLAG_SECT255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) dev->max_sectors = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ata_dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "SB600 AHCI: limiting to 255 sectors per cmd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) unsigned int ahci_dev_classify(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) tmp = readl(port_mmio + PORT_SIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) tf.lbah = (tmp >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) tf.lbam = (tmp >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) tf.lbal = (tmp >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) tf.nsect = (tmp) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return ata_dev_classify(&tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) EXPORT_SYMBOL_GPL(ahci_dev_classify);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) u32 opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dma_addr_t cmd_tbl_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) pp->cmd_slot[tag].opts = cpu_to_le32(opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) pp->cmd_slot[tag].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) int ahci_kick_engine(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) int busy, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* stop engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) rc = hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) goto out_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* need to do CLO?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * always do CLO if PMP is attached (AHCI-1.3 9.2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) busy = status & (ATA_BUSY | ATA_DRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (!busy && !sata_pmp_attached(ap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) goto out_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (!(hpriv->cap & HOST_CAP_CLO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) rc = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) goto out_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* perform CLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) tmp = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) tmp |= PORT_CMD_CLO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) writel(tmp, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (tmp & PORT_CMD_CLO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /* restart engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) out_restart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) EXPORT_SYMBOL_GPL(ahci_kick_engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct ata_taskfile *tf, int is_cmd, u16 flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) unsigned long timeout_msec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) const u32 cmd_fis_len = 5; /* five dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) u8 *fis = pp->cmd_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* prep the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ata_tf_to_fis(tf, pmp, is_cmd, fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* set port value for softreset of Port Multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) tmp = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) tmp |= pmp << PORT_FBS_DEV_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) writel(tmp, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) pp->fbs_last_dev = pmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /* issue & wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) writel(1, port_mmio + PORT_CMD_ISSUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (timeout_msec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) 0x1, 0x1, 1, timeout_msec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (tmp & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) ahci_kick_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) readl(port_mmio + PORT_CMD_ISSUE); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) int ahci_do_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) int pmp, unsigned long deadline,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) int (*check_ready)(struct ata_link *link))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) const char *reason = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) unsigned long now, msecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) bool fbs_disabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* prepare for SRST (AHCI-1.1 10.4.1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) rc = ahci_kick_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (rc && rc != -EOPNOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * clear PxFBS.EN to '0' prior to issuing software reset to devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * that is attached to port multiplier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (!ata_is_host_link(link) && pp->fbs_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ahci_disable_fbs(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) fbs_disabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ata_tf_init(link->device, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* issue the first H2D Register FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) msecs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) now = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (time_after(deadline, now))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) msecs = jiffies_to_msecs(deadline - now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) tf.ctl |= ATA_SRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) reason = "1st FIS failed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* spec says at least 5us, but be generous and sleep for 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) ata_msleep(ap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* issue the second H2D Register FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) tf.ctl &= ~ATA_SRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* wait for link to become ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) rc = ata_wait_after_reset(link, deadline, check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * Workaround for cases where link online status can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * be trusted. Treat device readiness timeout as link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * offline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ata_link_info(link, "device not ready, treating as offline\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) *class = ATA_DEV_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) } else if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* link occupied, -ENODEV too is an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) reason = "device not ready";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) *class = ahci_dev_classify(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* re-enable FBS if disabled before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (fbs_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ahci_enable_fbs(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) DPRINTK("EXIT, class=%u\n", *class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) ata_link_err(link, "softreset failed (%s)\n", reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) int ahci_check_ready(struct ata_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) void __iomem *port_mmio = ahci_port_base(link->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return ata_check_ready(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) EXPORT_SYMBOL_GPL(ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static int ahci_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int pmp = sata_srst_pmp(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) EXPORT_SYMBOL_GPL(ahci_do_softreset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static int ahci_bad_pmp_check_ready(struct ata_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) void __iomem *port_mmio = ahci_port_base(link->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * There is no need to check TFDATA if BAD PMP is found due to HW bug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) * which can save timeout delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (irq_status & PORT_IRQ_BAD_PMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return ata_check_ready(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) int pmp = sata_srst_pmp(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) u32 irq_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) rc = ahci_do_softreset(link, class, pmp, deadline,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ahci_bad_pmp_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * Soft reset fails with IPMS set when PMP is enabled but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * SATA HDD/ODD is connected to SATA port, do soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * again to port 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (rc == -EIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) irq_sts = readl(port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (irq_sts & PORT_IRQ_BAD_PMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) ata_link_warn(link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) "applying PMP SRST workaround "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) "and retrying\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) rc = ahci_do_softreset(link, class, 0, deadline,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) unsigned long deadline, bool *online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) /* clear D2H reception area to properly wait for D2H FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ata_tf_init(link->device, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) tf.command = ATA_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ata_tf_to_fis(&tf, 0, 0, d2h_fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) rc = sata_link_hardreset(link, timing, deadline, online,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (*online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) *class = ahci_dev_classify(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) EXPORT_SYMBOL_GPL(ahci_do_hardreset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static int ahci_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) bool online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return ahci_do_hardreset(link, class, deadline, &online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static void ahci_postreset(struct ata_link *link, unsigned int *class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) u32 new_tmp, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) ata_std_postreset(link, class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* Make sure port's ATAPI bit is set appropriately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) new_tmp = tmp = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (*class == ATA_DEV_ATAPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) new_tmp |= PORT_CMD_ATAPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) new_tmp &= ~PORT_CMD_ATAPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (new_tmp != tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) writel(new_tmp, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) readl(port_mmio + PORT_CMD); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) unsigned int si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) * Next, the S/G list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) for_each_sg(qc->sg, sg, qc->n_elem, si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) dma_addr_t addr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) u32 sg_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (!sata_pmp_attached(ap) || pp->fbs_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return ata_std_qc_defer(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return sata_pmp_qc_defer_cmd_switch(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) int is_atapi = ata_is_atapi(qc->tf.protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) void *cmd_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) u32 opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) const u32 cmd_fis_len = 5; /* five dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) unsigned int n_elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * Fill in command table information. First, the header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * a SATA Register - Host to Device command FIS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (is_atapi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) n_elem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (qc->flags & ATA_QCFLAG_DMAMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) n_elem = ahci_fill_sg(qc, cmd_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * Fill in command slot information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (qc->tf.flags & ATA_TFLAG_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) opts |= AHCI_CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (is_atapi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) static void ahci_fbs_dec_intr(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) u32 fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) int retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) BUG_ON(!pp->fbs_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) /* time to wait for DEC is not specified by AHCI spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * add a retry loop for safety.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) while ((fbs & PORT_FBS_DEC) && retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (fbs & PORT_FBS_DEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) dev_err(ap->host->dev, "failed to clear device error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct ata_eh_info *host_ehi = &ap->link.eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct ata_link *link = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) struct ata_queued_cmd *active_qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) struct ata_eh_info *active_ehi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) bool fbs_need_dec = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) u32 serror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) /* determine active link with error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (pp->fbs_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) u32 fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) int pmp = fbs >> PORT_FBS_DWE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) link = &ap->pmp_link[pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) fbs_need_dec = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) ata_for_each_link(link, ap, EDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (ata_link_active(link))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (!link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) link = &ap->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) active_qc = ata_qc_from_tag(ap, link->active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) active_ehi = &link->eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /* record irq stat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ata_ehi_clear_desc(host_ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /* AHCI needs SError cleared; otherwise, it might lock up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) ahci_scr_read(&ap->link, SCR_ERROR, &serror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) ahci_scr_write(&ap->link, SCR_ERROR, serror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) host_ehi->serror |= serror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* some controllers set IRQ_IF_ERR on device errors, ignore it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) irq_stat &= ~PORT_IRQ_IF_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (irq_stat & PORT_IRQ_TF_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* If qc is active, charge it; otherwise, the active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * link. There's no active qc on NCQ errors. It will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * be determined by EH by reading log page 10h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (active_qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) active_qc->err_mask |= AC_ERR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) active_ehi->err_mask |= AC_ERR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) host_ehi->serror &= ~SERR_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (irq_stat & PORT_IRQ_UNK_FIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) u32 *unk = pp->rx_fis + RX_FIS_UNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) active_ehi->err_mask |= AC_ERR_HSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) active_ehi->action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ata_ehi_push_desc(active_ehi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) "unknown FIS %08x %08x %08x %08x" ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) unk[0], unk[1], unk[2], unk[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) active_ehi->err_mask |= AC_ERR_HSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) active_ehi->action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) ata_ehi_push_desc(active_ehi, "incorrect PMP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) host_ehi->err_mask |= AC_ERR_HOST_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) host_ehi->action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ata_ehi_push_desc(host_ehi, "host bus error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (irq_stat & PORT_IRQ_IF_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (fbs_need_dec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) active_ehi->err_mask |= AC_ERR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) host_ehi->err_mask |= AC_ERR_ATA_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) host_ehi->action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) ata_ehi_push_desc(host_ehi, "interface fatal error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) ata_ehi_hotplugged(host_ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) ata_ehi_push_desc(host_ehi, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) irq_stat & PORT_IRQ_CONNECT ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) "connection status changed" : "PHY RDY changed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) /* okay, let's hand over to EH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (irq_stat & PORT_IRQ_FREEZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) else if (fbs_need_dec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ata_link_abort(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ahci_fbs_dec_intr(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) ata_port_abort(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static void ahci_handle_port_interrupt(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) void __iomem *port_mmio, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) struct ata_eh_info *ehi = &ap->link.eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) u32 qc_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) /* ignore BAD_PMP while resetting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (unlikely(resetting))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) status &= ~PORT_IRQ_BAD_PMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (sata_lpm_ignore_phy_events(&ap->link)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) status &= ~PORT_IRQ_PHYRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) if (unlikely(status & PORT_IRQ_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ahci_error_intr(ap, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (status & PORT_IRQ_SDB_FIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) /* If SNotification is available, leave notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) * handling to sata_async_notification(). If not,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) * emulate it by snooping SDB FIS RX area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) * Snooping FIS RX area is probably cheaper than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) * poking SNotification but some constrollers which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * implement SNotification, ICH9 for example, don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * store AN SDB FIS into receive area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (hpriv->cap & HOST_CAP_SNTF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) sata_async_notification(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) /* If the 'N' bit in word 0 of the FIS is set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * we just received asynchronous notification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * Tell libata about it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * Lack of SNotification should not appear in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) * ahci 1.2, so the workaround is unnecessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) * when FBS is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (pp->fbs_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) const __le32 *f = pp->rx_fis + RX_FIS_SDB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) u32 f0 = le32_to_cpu(f[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (f0 & (1 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) sata_async_notification(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /* pp->active_link is not reliable once FBS is enabled, both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * NCQ and non-NCQ commands may be in flight at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (pp->fbs_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (ap->qc_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) qc_active = readl(port_mmio + PORT_SCR_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) /* pp->active_link is valid iff any command is in flight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (ap->qc_active && pp->active_link->sactive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) qc_active = readl(port_mmio + PORT_SCR_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) qc_active = readl(port_mmio + PORT_CMD_ISSUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) rc = ata_qc_complete_multiple(ap, qc_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /* while resetting, invalid completions are expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (unlikely(rc < 0 && !resetting)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ehi->err_mask |= AC_ERR_HSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ehi->action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static void ahci_port_intr(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) status = readl(port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) writel(status, port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) ahci_handle_port_interrupt(ap, port_mmio, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) struct ata_port *ap = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) status = readl(port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) writel(status, port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) spin_lock(ap->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ahci_handle_port_interrupt(ap, port_mmio, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) spin_unlock(ap->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) VPRINTK("EXIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) unsigned int i, handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (!(irq_masked & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (ap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) ahci_port_intr(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) VPRINTK("port %u\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) VPRINTK("port %u (no irq)\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (ata_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) dev_warn(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) "interrupt on disabled port %u\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) unsigned int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) u32 irq_stat, irq_masked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) /* sigh. 0xffffffff is a valid return from h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) irq_stat = readl(mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if (!irq_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) irq_masked = irq_stat & hpriv->port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) rc = ahci_handle_port_intr(host, irq_masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) /* HOST_IRQ_STAT behaves as level triggered latch meaning that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) * it should be cleared after all the port events are cleared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) * otherwise, it will raise a spurious interrupt after each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * valid one. Please read section 10.6.2 of ahci 1.1 for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) * information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) * Also, use the unmasked value to clear interrupt as spurious
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) * pending event on a dummy port might cause screaming IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) writel(irq_stat, mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) VPRINTK("EXIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) return IRQ_RETVAL(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* Keep track of the currently active link. It will be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) * in completion path to determine whether NCQ phase is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) * progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) pp->active_link = qc->dev->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (ata_is_ncq(qc->tf.protocol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) u32 fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) writel(fbs, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) pp->fbs_last_dev = qc->dev->link->pmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) ahci_sw_activity(qc->dev->link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) EXPORT_SYMBOL_GPL(ahci_qc_issue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) struct ahci_port_priv *pp = qc->ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) u8 *rx_fis = pp->rx_fis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (pp->fbs_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * After a successful execution of an ATA PIO data-in command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * the device doesn't send D2H Reg FIS to update the TF and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * the host should take TF and E_Status from the preceding PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) * Setup FIS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) !(qc->flags & ATA_QCFLAG_FAILED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static void ahci_freeze(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) /* turn IRQ off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) writel(0, port_mmio + PORT_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static void ahci_thaw(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) tmp = readl(port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) writel(tmp, port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) /* turn IRQ back on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) void ahci_error_handler(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /* restart engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) sata_pmp_error_handler(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) if (!ata_dev_enabled(ap->link.device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) EXPORT_SYMBOL_GPL(ahci_error_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) /* make DMA engine forget about the failed command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (qc->flags & ATA_QCFLAG_FAILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ahci_kick_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) struct ata_device *dev = ap->link.device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) u32 devslp, dm, dito, mdat, deto, dito_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) unsigned int err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) devslp = readl(port_mmio + PORT_DEVSLP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (!(devslp & PORT_DEVSLP_DSP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) dev_info(ap->host->dev, "port does not support device sleep\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) /* disable device sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (!sleep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (devslp & PORT_DEVSLP_ADSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) writel(devslp & ~PORT_DEVSLP_ADSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) port_mmio + PORT_DEVSLP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) err_mask = ata_dev_set_feature(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) SETFEATURES_SATA_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) SATA_DEVSLP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (err_mask && err_mask != AC_ERR_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) ata_dev_warn(dev, "failed to disable DEVSLP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) dito = devslp_idle_timeout / (dm + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (dito > 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) dito = 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) /* device sleep was already enabled and same dito */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) rc = hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /* Use the nominal value 10 ms if the read MDAT is zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) * the nominal value of DETO is 20 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) ATA_LOG_DEVSLP_VALID_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) ATA_LOG_DEVSLP_MDAT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) if (!mdat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) mdat = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (!deto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) deto = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) mdat = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) deto = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /* Make dito, mdat, deto bits to 0s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) devslp &= ~GENMASK_ULL(24, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) (mdat << PORT_DEVSLP_MDAT_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) (deto << PORT_DEVSLP_DETO_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) PORT_DEVSLP_ADSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) writel(devslp, port_mmio + PORT_DEVSLP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) /* enable device sleep feature for the drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) err_mask = ata_dev_set_feature(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) SETFEATURES_SATA_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) SATA_DEVSLP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (err_mask && err_mask != AC_ERR_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ata_dev_warn(dev, "failed to enable DEVSLP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) static void ahci_enable_fbs(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) u32 fbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (!pp->fbs_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) if (fbs & PORT_FBS_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) pp->fbs_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) pp->fbs_last_dev = -1; /* initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) rc = hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) if (fbs & PORT_FBS_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) dev_info(ap->host->dev, "FBS is enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) pp->fbs_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) pp->fbs_last_dev = -1; /* initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) dev_err(ap->host->dev, "Failed to enable FBS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static void ahci_disable_fbs(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) u32 fbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) if (!pp->fbs_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if ((fbs & PORT_FBS_EN) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) pp->fbs_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) rc = hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) if (fbs & PORT_FBS_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) dev_err(ap->host->dev, "Failed to disable FBS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) dev_info(ap->host->dev, "FBS is disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) pp->fbs_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) static void ahci_pmp_attach(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) cmd = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) cmd |= PORT_CMD_PMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) writel(cmd, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) ahci_enable_fbs(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) pp->intr_mask |= PORT_IRQ_BAD_PMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) * We must not change the port interrupt mask register if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) * port is marked frozen, the value in pp->intr_mask will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) * restored later when the port is thawed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) * Note that during initialization, the port is marked as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) * frozen since the irq handler is not yet registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) if (!(ap->pflags & ATA_PFLAG_FROZEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) static void ahci_pmp_detach(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) ahci_disable_fbs(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) cmd = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) cmd &= ~PORT_CMD_PMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) writel(cmd, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) /* see comment above in ahci_pmp_attach() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) if (!(ap->pflags & ATA_PFLAG_FROZEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) int ahci_port_resume(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) ahci_rpm_get_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) ahci_power_up(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) ahci_start_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (sata_pmp_attached(ap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) ahci_pmp_attach(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) ahci_pmp_detach(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) EXPORT_SYMBOL_GPL(ahci_port_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) const char *emsg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) rc = ahci_deinit_port(ap, &emsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) ahci_power_down(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ata_port_err(ap, "%s (%d)\n", emsg, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) static int ahci_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) struct device *dev = ap->host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) struct ahci_port_priv *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) void *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) dma_addr_t mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) size_t dma_sz, rx_fis_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) if (!pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if (ap->host->n_ports > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) if (!pp->irq_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) devm_kfree(dev, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) snprintf(pp->irq_desc, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) "%s%d", dev_driver_string(dev), ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) /* check FBS capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) u32 cmd = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) if (cmd & PORT_CMD_FBSCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) pp->fbs_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) pp->fbs_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) dev_warn(dev, "port %d is not capable of FBS\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) if (pp->fbs_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) rx_fis_sz = AHCI_RX_FIS_SZ * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) dma_sz = AHCI_PORT_PRIV_DMA_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) rx_fis_sz = AHCI_RX_FIS_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) if (!mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) * First item in chunk of DMA memory: 32-slot command table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) * 32 bytes each in size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) pp->cmd_slot = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) pp->cmd_slot_dma = mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) mem += AHCI_CMD_SLOT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) mem_dma += AHCI_CMD_SLOT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) * Second item: Received-FIS area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) pp->rx_fis = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) pp->rx_fis_dma = mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) mem += rx_fis_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) mem_dma += rx_fis_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) * Third item: data area for storing a single command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) * and its scatter-gather table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) pp->cmd_tbl = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) pp->cmd_tbl_dma = mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) * Save off initial list of interrupts to be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) * This could be changed later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) pp->intr_mask = DEF_PORT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) * Switch to per-port locking in case each port has its own MSI vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) spin_lock_init(&pp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) ap->lock = &pp->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) ap->private_data = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) /* engage engines, captain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) return ahci_port_resume(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) static void ahci_port_stop(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) const char *emsg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) void __iomem *host_mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) /* de-initialize port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) rc = ahci_deinit_port(ap, &emsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) ata_port_warn(ap, "%s (%d)\n", emsg, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) * Clear GHC.IS to prevent stuck INTx after disabling MSI and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) * re-enabling INTx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) ahci_rpm_put_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) void ahci_print_info(struct ata_host *host, const char *scc_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) u32 vers, cap, cap2, impl, speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) const char *speed_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) vers = hpriv->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) cap = hpriv->cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) cap2 = hpriv->cap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) impl = hpriv->port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) speed = (cap >> 20) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) if (speed == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) speed_s = "1.5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) else if (speed == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) speed_s = "3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) else if (speed == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) speed_s = "6";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) speed_s = "?";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) dev_info(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) "AHCI %02x%02x.%02x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) (vers >> 24) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) (vers >> 16) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) (vers >> 8) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) vers & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) ((cap >> 8) & 0x1f) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) (cap & 0x1f) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) speed_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) impl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) scc_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) dev_info(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) "flags: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) "%s%s%s%s%s%s%s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) "%s%s%s%s%s%s%s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) "%s%s%s%s%s%s%s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) "%s%s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) cap & HOST_CAP_64 ? "64bit " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) cap & HOST_CAP_NCQ ? "ncq " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) cap & HOST_CAP_SNTF ? "sntf " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) cap & HOST_CAP_MPS ? "ilck " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) cap & HOST_CAP_SSS ? "stag " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) cap & HOST_CAP_ALPM ? "pm " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) cap & HOST_CAP_LED ? "led " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) cap & HOST_CAP_CLO ? "clo " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) cap & HOST_CAP_ONLY ? "only " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) cap & HOST_CAP_PMP ? "pmp " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) cap & HOST_CAP_FBS ? "fbs " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) cap & HOST_CAP_PIO_MULTI ? "pio " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) cap & HOST_CAP_SSC ? "slum " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) cap & HOST_CAP_PART ? "part " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) cap & HOST_CAP_CCC ? "ccc " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) cap & HOST_CAP_EMS ? "ems " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) cap & HOST_CAP_SXS ? "sxs " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) cap2 & HOST_CAP2_DESO ? "deso " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) cap2 & HOST_CAP2_SADM ? "sadm " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) cap2 & HOST_CAP2_SDS ? "sds " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) cap2 & HOST_CAP2_APST ? "apst " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) cap2 & HOST_CAP2_BOH ? "boh " : ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) EXPORT_SYMBOL_GPL(ahci_print_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) void ahci_set_em_messages(struct ahci_host_priv *hpriv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) struct ata_port_info *pi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) u8 messages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) u32 em_loc = readl(mmio + HOST_EM_LOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) u32 em_ctl = readl(mmio + HOST_EM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (messages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) /* store em_loc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) hpriv->em_loc = ((em_loc >> 16) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) hpriv->em_msg_type = messages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) pi->flags |= ATA_FLAG_EM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) if (!(em_ctl & EM_CTL_ALHD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) pi->flags |= ATA_FLAG_SW_ACTIVITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) EXPORT_SYMBOL_GPL(ahci_set_em_messages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) static int ahci_host_activate_multi_irqs(struct ata_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) struct scsi_host_template *sht)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) rc = ata_host_start(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) * Requests IRQs according to AHCI-1.1 when multiple MSIs were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) * allocated. That is one MSI per port, starting from @irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) struct ahci_port_priv *pp = host->ports[i]->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) int irq = hpriv->get_irq_vector(host, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) /* Do not receive interrupts sent by dummy ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) if (!pp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) disable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) 0, pp->irq_desc, host->ports[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) ata_port_desc(host->ports[i], "irq %d", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) return ata_host_register(host, sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) * ahci_host_activate - start AHCI host, request IRQs and register it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) * @host: target ATA host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) * @sht: scsi_host_template to use when registering the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) * Inherited from calling layer (may sleep).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) * RETURNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) * 0 on success, -errno otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) int irq = hpriv->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) if (hpriv->irq_handler &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) hpriv->irq_handler != ahci_single_level_irq_intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) dev_warn(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) if (!hpriv->get_irq_vector) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) dev_err(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) rc = ahci_host_activate_multi_irqs(host, sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) rc = ata_host_activate(host, irq, hpriv->irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) IRQF_SHARED, sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) EXPORT_SYMBOL_GPL(ahci_host_activate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) MODULE_AUTHOR("Jeff Garzik");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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