^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ata_piix.c - Intel PATA/SATA controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintained by: Tejun Heo <tj@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Please ALWAYS copy linux-ide@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * on emails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2003-2005 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 2003-2005 Jeff Garzik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright header from piix.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright (C) 2003 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Hardware documentation available at http://developer.intel.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Publicly available from Intel web site. Errata documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * is also publicly available. As an aide to anyone hacking on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * driver the list of errata that are relevant is below, going back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * PIIX4. Older device documentation is now a bit tricky to find.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The chipsets all follow very much the same design. The original Triton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * series chipsets do _not_ support independent device timings, but this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * is fixed in Triton II. With the odd mobile exception the chips then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * change little except in gaining more modes until SATA arrives. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * driver supports only the chips with independent timing (that is those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * for the early chip drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Errata of note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Unfixable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * PIIX4 errata #9 - Only on ultra obscure hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * ICH3 errata #13 - Not observed to affect real hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * by Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Things we must deal with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * PIIX4 errata #10 - BM IDE hang with non UDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * (must stop/start dma to recover)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 440MX errata #15 - As PIIX4 errata #10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * PIIX4 errata #15 - Must not read control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * during a PIO transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 440MX errata #13 - As PIIX4 errata #15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * ICH2 errata #21 - DMA mode 0 doesn't work right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * ICH0/1 errata #55 - As ICH2 errata #21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * ICH2 spec c #9 - Extra operations needed to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * drive hotswap [NOT YET SUPPORTED]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * and must be dword aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * ICH7 errata #16 - MWDMA1 timings are incorrect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Should have been BIOS fixed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 450NX: errata #19 - DMA hangs on old 450NX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * 450NX: errata #20 - DMA hangs on old 450NX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 450NX: errata #25 - Corruption with DMA on old 450NX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * ICH3 errata #15 - IDE deadlock under high load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * (BIOS must set dev 31 fn 0 bit 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * ICH3 errata #18 - Don't use native mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DRV_NAME "ata_piix"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DRV_VERSION "2.13"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ICH5_PMR = 0x90, /* address map register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ICH5_PCS = 0x92, /* port control and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PIIX_SIDPR_BAR = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PIIX_SIDPR_LEN = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PIIX_SIDPR_IDX = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PIIX_SIDPR_DATA = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PIIX_80C_PRI = (1 << 5) | (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PIIX_80C_SEC = (1 << 7) | (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* constants for mapping table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) P0 = 0, /* port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) P1 = 1, /* port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) P2 = 2, /* port 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) P3 = 3, /* port 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) IDE = -1, /* IDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) NA = -2, /* not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RV = -3, /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PIIX_AHCI_DEVICE = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* host->flags bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum piix_controller_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* controller IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) piix_pata_mwdma, /* PIIX3 MWDMA only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) piix_pata_33, /* PIIX4 at 33Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ich_pata_33, /* ICH up to UDMA 33 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ich_pata_66, /* ICH up to 66 Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ich_pata_100, /* ICH up to UDMA 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ich5_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ich6_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ich6m_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ich8_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ich8_2port_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ich8m_apple_sata, /* locks up on second port enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tolapai_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ich8_sata_snb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ich8_2port_sata_snb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ich8_2port_sata_byt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct piix_map_db {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const u16 port_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const int map[][4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct piix_host_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const int *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 saved_iocfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void __iomem *sidpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static unsigned int in_module_init = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct pci_device_id piix_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Intel PIIX3 for the 430HX etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* VMware ICH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Intel PIIX4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Intel PIIX4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Intel PIIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Intel ICH (i810, i815, i840) UDMA 66*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Intel ICH0 : UDMA 33*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Intel ICH2M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Intel ICH3M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Intel ICH3 (E7500/1) UDMA 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Intel ICH4-L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Intel ICH5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* C-ICH (i810E2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* ESB (855GME/875P + 6300ESB) UDMA 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* ICH6 (and 6) (i915) UDMA 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* ICH7/7-R (i945, i975) UDMA 100*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* ICH8 Mobile PATA Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* SATA ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* 82801EB (ICH5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* 82801EB (ICH5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* 6300ESB (ICH5 variant with broken PCS present bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* 6300ESB pretending RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* 82801FB/FW (ICH6/ICH6W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* 82801FR/FRW (ICH6R/ICH6RW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Attach iff the controller is in IDE mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* 82801GB/GR/GH (ICH7, identical to ICH6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* 82801GBM/GHM (ICH7M, identical to ICH6M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Enterprise Southbridge 2 (631xESB/632xESB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* SATA Controller 1 IDE (ICH8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* SATA Controller 2 IDE (ICH8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Mobile SATA Controller IDE (ICH8M), Apple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Mobile SATA Controller IDE (ICH8M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* SATA Controller IDE (ICH9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* SATA Controller IDE (ICH9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* SATA Controller IDE (ICH9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* SATA Controller IDE (ICH9M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* SATA Controller IDE (ICH9M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* SATA Controller IDE (ICH9M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* SATA Controller IDE (Tolapai) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* SATA Controller IDE (ICH10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* SATA Controller IDE (ICH10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* SATA Controller IDE (ICH10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* SATA Controller IDE (ICH10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* SATA Controller IDE (PCH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* SATA Controller IDE (PCH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* SATA Controller IDE (PCH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* SATA Controller IDE (PCH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* SATA Controller IDE (PCH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* SATA Controller IDE (PCH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* SATA Controller IDE (CPT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* SATA Controller IDE (CPT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* SATA Controller IDE (CPT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* SATA Controller IDE (CPT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* SATA Controller IDE (PBG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* SATA Controller IDE (PBG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* SATA Controller IDE (Panther Point) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* SATA Controller IDE (Panther Point) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* SATA Controller IDE (Panther Point) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* SATA Controller IDE (Panther Point) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* SATA Controller IDE (Lynx Point) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* SATA Controller IDE (Lynx Point) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* SATA Controller IDE (Lynx Point) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* SATA Controller IDE (Lynx Point) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* SATA Controller IDE (Lynx Point-LP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* SATA Controller IDE (Lynx Point-LP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* SATA Controller IDE (Lynx Point-LP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* SATA Controller IDE (Lynx Point-LP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* SATA Controller IDE (DH89xxCC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* SATA Controller IDE (Avoton) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* SATA Controller IDE (Avoton) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* SATA Controller IDE (Avoton) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* SATA Controller IDE (Avoton) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* SATA Controller IDE (Wellsburg) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* SATA Controller IDE (Wellsburg) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* SATA Controller IDE (Wellsburg) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* SATA Controller IDE (Wellsburg) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* SATA Controller IDE (BayTrail) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* SATA Controller IDE (Coleto Creek) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* SATA Controller IDE (9 Series) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 0x8086, 0x8c88, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* SATA Controller IDE (9 Series) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 0x8086, 0x8c89, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* SATA Controller IDE (9 Series) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 0x8086, 0x8c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* SATA Controller IDE (9 Series) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 0x8086, 0x8c81, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct piix_map_db ich5_map_db = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .port_enable = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* PM PS SM SS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { P0, NA, P1, NA }, /* 000b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { P1, NA, P0, NA }, /* 001b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { RV, RV, RV, RV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { RV, RV, RV, RV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { P0, P1, IDE, IDE }, /* 100b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { P1, P0, IDE, IDE }, /* 101b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { IDE, IDE, P0, P1 }, /* 110b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { IDE, IDE, P1, P0 }, /* 111b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct piix_map_db ich6_map_db = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .port_enable = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* PM PS SM SS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { P0, P2, P1, P3 }, /* 00b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { IDE, IDE, P1, P3 }, /* 01b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { P0, P2, IDE, IDE }, /* 10b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { RV, RV, RV, RV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct piix_map_db ich6m_map_db = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .port_enable = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Map 01b isn't specified in the doc but some notebooks use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * it anyway. MAP 01b have been spotted on both ICH6M and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * ICH7M.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* PM PS SM SS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { P0, P2, NA, NA }, /* 00b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { IDE, IDE, P1, P3 }, /* 01b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { P0, P2, IDE, IDE }, /* 10b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { RV, RV, RV, RV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct piix_map_db ich8_map_db = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .port_enable = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* PM PS SM SS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { RV, RV, RV, RV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { RV, RV, RV, RV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct piix_map_db ich8_2port_map_db = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .port_enable = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* PM PS SM SS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { P0, NA, P1, NA }, /* 00b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { RV, RV, RV, RV }, /* 01b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { RV, RV, RV, RV }, /* 10b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { RV, RV, RV, RV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct piix_map_db ich8m_apple_map_db = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .port_enable = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* PM PS SM SS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { P0, NA, NA, NA }, /* 00b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { RV, RV, RV, RV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { P0, P2, IDE, IDE }, /* 10b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { RV, RV, RV, RV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct piix_map_db tolapai_map_db = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .port_enable = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* PM PS SM SS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { P0, NA, P1, NA }, /* 00b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { RV, RV, RV, RV }, /* 01b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { RV, RV, RV, RV }, /* 10b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { RV, RV, RV, RV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct piix_map_db *piix_map_db_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) [ich5_sata] = &ich5_map_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) [ich6_sata] = &ich6_map_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) [ich6m_sata] = &ich6m_map_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) [ich8_sata] = &ich8_map_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) [ich8_2port_sata] = &ich8_2port_map_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [ich8m_apple_sata] = &ich8m_apple_map_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) [tolapai_sata] = &tolapai_map_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) [ich8_sata_snb] = &ich8_map_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [ich8_2port_sata_snb] = &ich8_2port_map_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [ich8_2port_sata_byt] = &ich8_2port_map_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct pci_bits piix_enable_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct ich_laptop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u16 subvendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u16 subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * List of laptops that use short cables rather than 80 wire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const struct ich_laptop ich_laptop[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* devid, subvendor, subdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { 0x24CA, 0x10CF, 0x11AB }, /* ICH4M on Fujitsu-Siemens Lifebook S6120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* end marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int piix_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!(ap->flags & PIIX_FLAG_PIO16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ata_bmdma_port_start(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * ich_pata_cable_detect - Probe host controller cable detect info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * @ap: Port for which cable detect info is desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Read 80c cable indicator from ATA PCI device's PCI config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * register. This register is normally set by firmware (BIOS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int ich_pata_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct piix_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) const struct ich_laptop *lap = &ich_laptop[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Check for specials */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) while (lap->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (lap->device == pdev->device &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) lap->subvendor == pdev->subsystem_vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) lap->subdevice == pdev->subsystem_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return ATA_CBL_PATA40_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) lap++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* check BIOS cable detect results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if ((hpriv->saved_iocfg & mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * piix_pata_prereset - prereset for PATA host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * @link: Target link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static DEFINE_SPINLOCK(piix_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u8 pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct pci_dev *dev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int is_slave = (adev->devno != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int master_port= ap->port_no ? 0x42 : 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned int slave_port = 0x44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u16 master_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 slave_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u8 udma_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * See Intel Document 298600-004 for the timing programing rules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * for ICH controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const /* ISP RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u8 timings[][2] = { { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { 2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { 2, 3 }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (pio >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) control |= 1; /* TIME1 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ata_pio_need_iordy(adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) control |= 2; /* IE enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Intel specifies that the PPE functionality is for disk only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (adev->class == ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) control |= 4; /* PPE enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * If the drive MWDMA is faster than it can do PIO then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * we must force PIO into PIO0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (adev->pio_mode < XFER_PIO_0 + pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Enable DMA timing only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) control |= 8; /* PIO cycles in PIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) spin_lock_irqsave(&piix_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* PIO configuration clears DTE unconditionally. It will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * programmed in set_dmamode which is guaranteed to be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * after set_piomode if any DMA mode is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pci_read_config_word(dev, master_port, &master_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (is_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* clear TIME1|IE1|PPE1|DTE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) master_data &= 0xff0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* enable PPE1, IE1 and TIME1 as needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) master_data |= (control << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pci_read_config_byte(dev, slave_port, &slave_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) slave_data &= (ap->port_no ? 0x0f : 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Load the timing nibble for this slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) << (ap->port_no ? 4 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) master_data &= 0xccf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Enable PPE, IE and TIME as appropriate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) master_data |= control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* load ISP and RCT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) master_data |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) (timings[pio][0] << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) (timings[pio][1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Enable SITRE (separate slave timing register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) master_data |= 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pci_write_config_word(dev, master_port, master_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pci_write_config_byte(dev, slave_port, slave_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Ensure the UDMA bit is off - it will be turned back on if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) UDMA is selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ap->udma_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pci_read_config_byte(dev, 0x48, &udma_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pci_write_config_byte(dev, 0x48, udma_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) spin_unlock_irqrestore(&piix_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * piix_set_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * @adev: Drive in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * Set PIO mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * do_pata_set_dmamode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * @adev: Drive in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * @isich: set if the chip is an ICH device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Set UDMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct pci_dev *dev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u8 speed = adev->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int devid = adev->devno + 2 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u8 udma_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (speed >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned int udma = speed - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u16 udma_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u16 ideconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int u_clock, u_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) spin_lock_irqsave(&piix_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) pci_read_config_byte(dev, 0x48, &udma_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * UDMA is handled by a combination of clock switching and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * selection of dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * Handy rule: Odd modes are UDMATIMx 01, even are 02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * except UDMA0 which is 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u_speed = min(2 - (udma & 1), udma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (udma == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u_clock = 0x1000; /* 100Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) else if (udma > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u_clock = 1; /* 66Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u_clock = 0; /* 33Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) udma_enable |= (1 << devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Load the CT/RP selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pci_read_config_word(dev, 0x4A, &udma_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) udma_timing &= ~(3 << (4 * devid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) udma_timing |= u_speed << (4 * devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) pci_write_config_word(dev, 0x4A, udma_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (isich) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Select a 33/66/100Mhz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pci_read_config_word(dev, 0x54, &ideconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ideconf &= ~(0x1001 << devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ideconf |= u_clock << devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* For ICH or later we should set bit 10 for better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) performance (WR_PingPong_En) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) pci_write_config_word(dev, 0x54, ideconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pci_write_config_byte(dev, 0x48, udma_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) spin_unlock_irqrestore(&piix_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* MWDMA is driven by the PIO timings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned int mwdma = speed - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) const unsigned int needed_pio[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int pio = needed_pio[mwdma] - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* XFER_PIO_0 is never used currently */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) piix_set_timings(ap, adev, pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * piix_set_dmamode - Initialize host controller PATA DMA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * @adev: um
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * Set MW/UDMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) do_pata_set_dmamode(ap, adev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * ich_set_dmamode - Initialize host controller PATA DMA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * @adev: um
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * Set MW/UDMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) do_pata_set_dmamode(ap, adev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * Serial ATA Index/Data Pair Superset Registers access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * Beginning from ICH8, there's a sane way to access SCRs using index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * and data register pair located at BAR5 which means that we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * separate SCRs for master and slave. This is handled using libata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * slave_link facility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const int piix_sidx_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [SCR_STATUS] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [SCR_ERROR] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [SCR_CONTROL] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct piix_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) hpriv->sidpr + PIIX_SIDPR_IDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int piix_sidpr_scr_read(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned int reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct piix_host_priv *hpriv = link->ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (reg >= ARRAY_SIZE(piix_sidx_map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) piix_sidpr_sel(link, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int piix_sidpr_scr_write(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) unsigned int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct piix_host_priv *hpriv = link->ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (reg >= ARRAY_SIZE(piix_sidx_map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) piix_sidpr_sel(link, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return sata_link_scr_lpm(link, policy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static bool piix_irq_check(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (unlikely(!ap->ioaddr.bmdma_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int piix_broken_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const struct dmi_system_id sysids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .ident = "TECRA M3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .ident = "TECRA M3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .ident = "TECRA M3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) DMI_MATCH(DMI_OEM_STRING, "Tecra M3,"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .ident = "TECRA M4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .ident = "TECRA M4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .ident = "TECRA M5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .ident = "TECRA M6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .ident = "TECRA M7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .ident = "TECRA A8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .ident = "Satellite R20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .ident = "Satellite R25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .ident = "Satellite U200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .ident = "Satellite U200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .ident = "Satellite Pro U200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .ident = "Satellite U205",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .ident = "SATELLITE U205",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .ident = "Satellite Pro A120",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .ident = "Portege M500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .ident = "VGN-BX297XP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (dmi_check_system(sysids))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* TECRA M4 sometimes forgets its identify and reports bogus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * DMI information. As the bogus information is a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * generic, match as many entries as possible. This manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * matching is necessary because dmi_system_id.matches is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * limited to four entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dmi_match(DMI_PRODUCT_NAME, "000000") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dmi_match(DMI_PRODUCT_VERSION, "000000") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dmi_match(DMI_BOARD_NAME, "Portable PC") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dmi_match(DMI_BOARD_VERSION, "Version A0"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) rc = ata_host_suspend(host, mesg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* Some braindamaged ACPI suspend implementations expect the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * controller to be awake on entry; otherwise, it burns cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * cycles and power trying to do something to the sleeping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * beauty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* mark its power state as "unknown", since we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * know if e.g. the BIOS will change its device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * when we suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (pdev->current_state == PCI_D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) pdev->current_state = PCI_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* tell resume that it's waking up from broken suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) host->flags |= PIIX_HOST_BROKEN_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ata_pci_device_do_suspend(pdev, mesg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static int piix_pci_device_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* PCI device wasn't disabled during suspend. Use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * pci_reenable_device() to avoid affecting the enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) rc = pci_reenable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) "failed to enable device after resume (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static u8 piix_vmw_bmdma_status(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static struct scsi_host_template piix_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static struct ata_port_operations piix_sata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .inherits = &ata_bmdma32_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .sff_irq_check = piix_irq_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .port_start = piix_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static struct ata_port_operations piix_pata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .inherits = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .set_piomode = piix_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .set_dmamode = piix_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .prereset = piix_pata_prereset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static struct ata_port_operations piix_vmw_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .inherits = &piix_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .bmdma_status = piix_vmw_bmdma_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static struct ata_port_operations ich_pata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .inherits = &piix_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .cable_detect = ich_pata_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .set_dmamode = ich_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static struct device_attribute *piix_sidpr_shost_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) &dev_attr_link_power_management_policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static struct scsi_host_template piix_sidpr_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .shost_attrs = piix_sidpr_shost_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static struct ata_port_operations piix_sidpr_sata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .inherits = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .hardreset = sata_std_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .scr_read = piix_sidpr_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .scr_write = piix_sidpr_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .set_lpm = piix_sidpr_set_lpm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static struct ata_port_info piix_port_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) [piix_pata_mwdma] = /* PIIX3 MWDMA only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .flags = PIIX_PATA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .port_ops = &piix_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) [piix_pata_33] = /* PIIX4 at 33MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .flags = PIIX_PATA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .port_ops = &piix_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .flags = PIIX_PATA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .port_ops = &ich_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) [ich_pata_66] = /* ICH controllers up to 66MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .flags = PIIX_PATA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .port_ops = &ich_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) [ich_pata_100] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .mwdma_mask = ATA_MWDMA12_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .port_ops = &ich_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) [ich_pata_100_nomwdma1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .mwdma_mask = ATA_MWDMA2_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .port_ops = &ich_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) [ich5_sata] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .flags = PIIX_SATA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .port_ops = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) [ich6_sata] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .flags = PIIX_SATA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .port_ops = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) [ich6m_sata] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .flags = PIIX_SATA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .port_ops = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) [ich8_sata] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .port_ops = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) [ich8_2port_sata] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .port_ops = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) [tolapai_sata] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .flags = PIIX_SATA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .port_ops = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) [ich8m_apple_sata] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .flags = PIIX_SATA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .port_ops = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) [piix_pata_vmw] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .flags = PIIX_PATA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .port_ops = &piix_vmw_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * some Sandybridge chipsets have broken 32 mode up to now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) [ich8_sata_snb] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .port_ops = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) [ich8_2port_sata_snb] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) | PIIX_FLAG_PIO16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .port_ops = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) [ich8_2port_sata_byt] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .port_ops = &piix_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define AHCI_PCI_BAR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define AHCI_GLOBAL_CTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define AHCI_ENABLE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static int piix_disable_ahci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* BUG: pci_enable_device has not yet been called. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * works because this device is usually set up by BIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) !pci_resource_len(pdev, AHCI_PCI_BAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (!mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (tmp & AHCI_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) tmp &= ~AHCI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (tmp & AHCI_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pci_iounmap(pdev, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * piix_check_450nx_errata - Check for problem 450NX setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * @ata_dev: the PCI device to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * Check for the present of 450NX errata #19 and errata #25. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * they are found return an error code so we can turn off DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static int piix_check_450nx_errata(struct pci_dev *ata_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct pci_dev *pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) u16 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) int no_piix_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* Look for 450NX PXB. Check for problem configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) A PCI quirk checks bit 6 already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) pci_read_config_word(pdev, 0x41, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Only on the original revision: IDE DMA can hang */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (pdev->revision == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) no_piix_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* On all revisions below 5 PXB bus lock must be disabled for IDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) else if (cfg & (1<<14) && pdev->revision < 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) no_piix_dma = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (no_piix_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) dev_warn(&ata_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) "450NX errata present, disabling IDE DMA%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) no_piix_dma == 2 ? " - a BIOS update may resolve this"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return no_piix_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static void piix_init_pcs(struct ata_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) const struct piix_map_db *map_db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct pci_dev *pdev = to_pci_dev(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) u16 pcs, new_pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) pci_read_config_word(pdev, ICH5_PCS, &pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) new_pcs = pcs | map_db->port_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (new_pcs != pcs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) pci_write_config_word(pdev, ICH5_PCS, new_pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static const int *piix_init_sata_map(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct ata_port_info *pinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) const struct piix_map_db *map_db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) const int *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) int i, invalid_map = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) u8 map_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) char buf[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) char *p = buf, *end = buf + sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) pci_read_config_byte(pdev, ICH5_PMR, &map_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) map = map_db->map[map_value & map_db->mask];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) switch (map[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) case RV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) invalid_map = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) p += scnprintf(p, end - p, " XX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) case NA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) p += scnprintf(p, end - p, " --");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) case IDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) WARN_ON((i & 1) || map[i + 1] != IDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) pinfo[i / 2] = piix_port_info[ich_pata_100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) p += scnprintf(p, end - p, " IDE IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) p += scnprintf(p, end - p, " P%d", map[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (i & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dev_info(&pdev->dev, "MAP [%s ]\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (invalid_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static bool piix_no_sidpr(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct pci_dev *pdev = to_pci_dev(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * Samsung DB-P70 only has three ATA ports exposed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * curiously the unconnected first port reports link online
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * while not responding to SRST protocol causing excessive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * detection delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * Unfortunately, the system doesn't carry enough DMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * information to identify the machine but does have subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) * vendor and device set. As it's unclear whether the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * subsystem vendor/device is used only for this specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * board, the port can't be disabled solely with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * information; however, turning off SIDPR access works around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * the problem. Turn it off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * This problem is reported in bnc#441240.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * https://bugzilla.novell.com/show_bug.cgi?id=441420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) pdev->subsystem_device == 0xb049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) dev_warn(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) "Samsung DB-P70 detected, disabling SIDPR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static int piix_init_sidpr(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct pci_dev *pdev = to_pci_dev(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct piix_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct ata_link *link0 = &host->ports[0]->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) u32 scontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /* check for availability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (hpriv->map[i] == IDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* is it blacklisted? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (piix_no_sidpr(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /* SCR access via SIDPR doesn't work on some configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * Give it a test drive by inhibiting power save modes which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * we'll do anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* if IPM is already 3, SCR access is probably working. Don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * un-inhibit power save modes as BIOS might have inhibited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * them for a reason.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if ((scontrol & 0xf00) != 0x300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) scontrol |= 0x300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if ((scontrol & 0xf00) != 0x300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) dev_info(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) "SCR access via SIDPR is available but doesn't work\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* okay, SCRs available, set ops and ask libata for slave_link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ap->ops = &piix_sidpr_sata_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (ap->flags & ATA_FLAG_SLAVE_POSS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) rc = ata_slave_link_init(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static void piix_iocfg_bit18_quirk(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static const struct dmi_system_id sysids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /* Clevo M570U sets IOCFG bit 18 if the cdrom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * isn't used to boot the system which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * disables the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .ident = "M570U",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct pci_dev *pdev = to_pci_dev(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct piix_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (!dmi_check_system(sysids))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* The datasheet says that bit 18 is NOOP but certain systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * seem to use it to disable a channel. Clear the bit on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * affected systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (hpriv->saved_iocfg & (1 << 18)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) pci_write_config_dword(pdev, PIIX_IOCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) hpriv->saved_iocfg & ~(1 << 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static bool piix_broken_system_poweroff(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static const struct dmi_system_id broken_systems[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .ident = "HP Compaq 2510p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* PCI slot number of the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .driver_data = (void *)0x1FUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .ident = "HP Compaq nc6000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* PCI slot number of the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .driver_data = (void *)0x1FUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (dmi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) unsigned long slot = (unsigned long)dmi->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* apply the quirk only to on-board controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return slot == PCI_SLOT(pdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static int prefer_ms_hyperv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) module_param(prefer_ms_hyperv, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) MODULE_PARM_DESC(prefer_ms_hyperv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) "Prefer Hyper-V paravirtualization drivers instead of ATA, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) "0 - Use ATA drivers, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) "1 (Default) - Use the paravirtualization drivers.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static void piix_ignore_devices_quirk(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #if IS_ENABLED(CONFIG_HYPERV_STORAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static const struct dmi_system_id ignore_hyperv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /* On Hyper-V hypervisors the disks are exposed on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) * both the emulated SATA controller and on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * paravirtualised drivers. The CD/DVD devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * are only exposed on the emulated controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * Request we ignore ATA devices on this host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .ident = "Hyper-V Virtual Machine",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) DMI_MATCH(DMI_SYS_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) "Microsoft Corporation"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static const struct dmi_system_id allow_virtual_pc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* In MS Virtual PC guests the DMI ident is nearly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) * identical to a Hyper-V guest. One difference is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) * product version which is used here to identify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) * a Virtual PC guest. This entry allows ata_piix to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) * drive the emulated hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .ident = "MS Virtual PC 2007",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) DMI_MATCH(DMI_SYS_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) "Microsoft Corporation"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (ignore && !allow && prefer_ms_hyperv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) host->flags |= ATA_HOST_IGNORE_ATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) dev_info(host->dev, "%s detected, ATA device ignore set\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) ignore->ident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * piix_init_one - Register PIIX ATA PCI device with kernel services
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * @pdev: PCI device to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * @ent: Entry in piix_pci_tbl matching with @pdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * Called from kernel PCI layer. We probe for combined mode (sigh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * and then hand over control to libata, for it to do the rest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * Inherited from PCI layer (may sleep).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) * RETURNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) * Zero on success, or -ERRNO value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct ata_port_info port_info[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct scsi_host_template *sht = &piix_sht;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) unsigned long port_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct piix_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* no hotplugging support for later devices (FIXME) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (!in_module_init && ent->driver_data >= ich5_sata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (piix_broken_system_poweroff(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) piix_port_info[ent->driver_data].flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) ATA_FLAG_NO_POWEROFF_SPINDOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ATA_FLAG_NO_HIBERNATE_SPINDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) "on poweroff and hibernation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) port_info[0] = piix_port_info[ent->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) port_info[1] = piix_port_info[ent->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) port_flags = port_info[0].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /* enable device and prepare host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (!hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* Save IOCFG, this will be used for cable detection, quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) * detection and restoration on detach. This is necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) * because some ACPI implementations mess up cable related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * bits on _STM. Reported on kernel bz#11879.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) /* ICH6R may be driven by either ata_piix or ahci driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) * regardless of BIOS configuration. Make sure AHCI mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) * off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) rc = piix_disable_ahci(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /* SATA map init can change port_info, do it before prepping host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (port_flags & ATA_FLAG_SATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) hpriv->map = piix_init_sata_map(pdev, port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) piix_map_db_table[ent->driver_data]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) host->private_data = hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) /* initialize controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (port_flags & ATA_FLAG_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) rc = piix_init_sidpr(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (host->ports[0]->ops == &piix_sidpr_sata_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) sht = &piix_sidpr_sht;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* apply IOCFG bit18 quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) piix_iocfg_bit18_quirk(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* On ICH5, some BIOSen disable the interrupt using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * On ICH6, this bit has the same effect, but only when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * MSI is disabled (and it is disabled, as we don't use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) * message-signalled interrupts currently).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (port_flags & PIIX_FLAG_CHECKINTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) pci_intx(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (piix_check_450nx_errata(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /* This writes into the master table but it does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) really matter for this errata as we will apply it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) all the PIIX devices on the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) host->ports[0]->mwdma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) host->ports[0]->udma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) host->ports[1]->mwdma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) host->ports[1]->udma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) host->flags |= ATA_HOST_PARALLEL_SCAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* Allow hosts to specify device types to ignore when scanning. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) piix_ignore_devices_quirk(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) static void piix_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct piix_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) ata_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static struct pci_driver piix_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .id_table = piix_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .probe = piix_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .remove = piix_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .suspend = piix_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .resume = piix_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static int __init piix_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) DPRINTK("pci_register_driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) rc = pci_register_driver(&piix_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) in_module_init = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) DPRINTK("done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static void __exit piix_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) pci_unregister_driver(&piix_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) module_init(piix_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) module_exit(piix_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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