^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * ata_generic.c - Generic PATA/SATA controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2005 Red Hat Inc, all rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Elements from ide/pci/generic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Portions (C) Copyright 2002 Red Hat Inc <alan@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Driver for PCI IDE interfaces implementing the standard bus mastering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * interface functionality. This assumes the BIOS did the drive set up and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * tuning for us. By default we do not grab all IDE class devices as they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * may have other drivers or need fixups to avoid problems. Instead we keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * a default list of stuff without documentation/driver that appears to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRV_NAME "ata_generic"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRV_VERSION "0.2.15"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * A generic parallel ATA driver using libata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ATA_GEN_CLASS_MATCH = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ATA_GEN_FORCE_DMA = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ATA_GEN_INTEL_IDER = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * generic_set_mode - mode setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @link: link to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @unused: returned device on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Use a non standard set_mode function. We don't want to be tuned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * The BIOS configured everything. Our job is not to fiddle. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * read the dma enabled bits from the PCI configuration of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * and respect them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int generic_set_mode(struct ata_link *link, struct ata_device **unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const struct pci_device_id *id = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int dma_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (id->driver_data & ATA_GEN_FORCE_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dma_enabled = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) } else if (ap->ioaddr.bmdma_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Bits 5 and 6 indicate if DMA is active on master/slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ata_for_each_dev(dev, link, ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* We don't really care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev->pio_mode = XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dev->dma_mode = XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* We do need the right mode information for DMA or PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) and this comes from the current configuration flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (dma_enabled & (1 << (5 + dev->devno))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int xfer_mask = ata_id_xfermask(dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (xfer_mask & (ATA_MASK_MWDMA | ATA_MASK_UDMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) name = ata_mode_string(xfer_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* SWDMA perhaps? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) name = "DMA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) xfer_mask |= ata_xfer_mode2mask(XFER_MW_DMA_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ata_dev_info(dev, "configured for %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev->xfer_mode = ata_xfer_mask2mode(xfer_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev->xfer_shift = ata_xfer_mode2shift(dev->xfer_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev->flags &= ~ATA_DFLAG_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ata_dev_info(dev, "configured for PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev->xfer_mode = XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev->xfer_shift = ATA_SHIFT_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev->flags |= ATA_DFLAG_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct scsi_host_template generic_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct ata_port_operations generic_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .cable_detect = ata_cable_unknown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .set_mode = generic_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int all_generic_ide; /* Set to claim all devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * is_intel_ider - identify intel IDE-R devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Distinguish Intel IDE-R controller devices from other Intel IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * devices. IDE-R devices have no timing registers and are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * most respects virtual. They should be driven by the ata_generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * IDE-R devices have PCI offset 0xF8.L as zero, later Intel ATA has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * it non zero. All Intel ATA has 0x40 writable (timing), but it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * not writable on IDE-R devices (this is guaranteed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int is_intel_ider(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* For Intel IDE the value at 0xF8 is only zero on IDE-R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) interfaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Check the manufacturing ID, it will be zero for IDE-R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pci_read_config_dword(dev, 0xF8, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Not IDE-R: punt so that ata_(old)piix gets it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* 0xF8 will also be zero on some early Intel IDE devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) but they will have a sane timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pci_read_config_word(dev, 0x40, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (t != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Finally check if the timing register is writable so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) we eliminate any early devices hot-docked in a docking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) station */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pci_write_config_word(dev, 0x40, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pci_read_config_word(dev, 0x40, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pci_write_config_word(dev, 0x40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * ata_generic_init - attach generic IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @dev: PCI device found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @id: match entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Called each time a matching IDE interface is found. We check if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * interface is one we wish to claim and if so we perform any chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * specific hacks then let the ATA layer do the heavy lifting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .port_ops = &generic_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const struct ata_port_info *ppi[] = { &info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Don't use the generic entry unless instructed to do so */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if ((id->driver_data & ATA_GEN_CLASS_MATCH) && all_generic_ide == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if ((id->driver_data & ATA_GEN_INTEL_IDER) && !all_generic_ide)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!is_intel_ider(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Devices that need care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (dev->vendor == PCI_VENDOR_ID_UMC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) (!(PCI_FUNC(dev->devfn) & 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (dev->vendor == PCI_VENDOR_ID_OPTI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev->device == PCI_DEVICE_ID_OPTI_82C558 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (!(PCI_FUNC(dev->devfn) & 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Don't re-enable devices in generic mode or we will break some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) motherboards with disabled and unused IDE controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pci_read_config_word(dev, PCI_COMMAND, &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!(command & PCI_COMMAND_IO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (dev->vendor == PCI_VENDOR_ID_AL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ata_pci_bmdma_clear_simplex(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (dev->vendor == PCI_VENDOR_ID_ATI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int rc = pcim_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pcim_pin_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ata_pci_bmdma_init_one(dev, ppi, &generic_sht, (void *)id, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct pci_device_id ata_generic[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { PCI_DEVICE(PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { PCI_DEVICE(PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { PCI_DEVICE(PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { PCI_DEVICE(PCI_VENDOR_ID_CENATEK,PCI_DEVICE_ID_CENATEK_IDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .driver_data = ATA_GEN_FORCE_DMA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #if !defined(CONFIG_PATA_TOSHIBA) && !defined(CONFIG_PATA_TOSHIBA_MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_5), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Intel, IDE class device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .driver_data = ATA_GEN_INTEL_IDER },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Must come last. If you add entries adjust this table appropriately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .driver_data = ATA_GEN_CLASS_MATCH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct pci_driver ata_generic_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .id_table = ata_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .probe = ata_generic_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .resume = ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) module_pci_driver(ata_generic_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MODULE_DESCRIPTION("low-level driver for generic ATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_DEVICE_TABLE(pci, ata_generic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) module_param(all_generic_ide, int, 0);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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