^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AppliedMicro X-Gene SoC SATA Host Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Loc Ho <lho@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Tuan Phan <tphan@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Suman Tripathi <stripathi@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * NOTE: PM support is not currently available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRV_NAME "xgene-ahci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Max # of disk per a controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX_AHCI_CHN_PERCTR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* MUX CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SATA_ENET_CONFIG_REG 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CFG_SATA_ENET_SELECT_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* SATA core host controller CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SLVRDERRATTRIBUTES 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SLVWRERRATTRIBUTES 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MSTRDERRATTRIBUTES 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MSTWRERRATTRIBUTES 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BUSCTLREG 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IOFMSTRWAUX 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define INTSTATUSMASK 0x0000002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ERRINTSTATUS 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ERRINTSTATUSMASK 0x00000034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* SATA host AHCI CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PORTCFG 0x000000a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PORTADDR_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PORTPHY1CFG 0x000000a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PORTPHY2CFG 0x000000ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PORTPHY3CFG 0x000000b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PORTPHY4CFG 0x000000b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PORTPHY5CFG 0x000000b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCTL0 0x0000012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PORTPHY5CFG_RTCHG_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PORTAXICFG 0x000000bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PORTAXICFG_OUTTRANS_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PORTRANSCFG 0x000000c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PORTRANSCFG_RXWM_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* SATA host controller AXI CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define INT_SLV_TMOMASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* SATA diagnostic CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CFG_MEM_RAM_SHUTDOWN 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BLOCK_MEM_RDY 0x00000074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Max retry for link down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MAX_LINK_DOWN_RETRY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) enum xgene_ahci_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) XGENE_AHCI_V1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) XGENE_AHCI_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct xgene_ahci_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 class[MAX_AHCI_CHN_PERCTR]; /* tracking the class of device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *csr_core; /* Core CSR address of IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __iomem *csr_diag; /* Diag CSR address of IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *csr_axi; /* AXI CSR address of IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *csr_mux; /* MUX CSR address of IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_dbg(ctx->dev, "Release memory from shutdown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) msleep(1); /* reset may take up to 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_err(ctx->dev, "failed to release memory from shutdown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * xgene_ahci_poll_reg_val- Poll a register on a specific value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @ap : ATA port of interest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @reg : Register of interest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @val : Value to be attained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @interval : waiting interval for polling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @timeout : timeout for achieving the value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int xgene_ahci_poll_reg_val(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *reg, unsigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int val, unsigned long interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long deadline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tmp = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) deadline = ata_deadline(jiffies, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) while (tmp != val && time_before(jiffies, deadline)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ata_msleep(ap, interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tmp = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * xgene_ahci_restart_engine - Restart the dma engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @ap : ATA port of interest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Waits for completion of multiple commands and restarts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * the DMA engine inside the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int xgene_ahci_restart_engine(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 fbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * In case of PMP multiple IDENTIFY DEVICE commands can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * issued inside PxCI. So need to poll PxCI for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * completion of outstanding IDENTIFY DEVICE commands before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * we restart the DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (xgene_ahci_poll_reg_val(ap, port_mmio +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PORT_CMD_ISSUE, 0x0, 1, 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ahci_start_fis_rx(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Enable the PxFBS.FBS_EN bit as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * gets cleared due to stopping the engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (pp->fbs_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * xgene_ahci_qc_issue - Issue commands to the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @qc: Command to issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * clear the BSY bit after receiving the PIO setup FIS. This results in the dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * state machine goes into the CMFatalErrorUpdate state and locks up. By
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * restarting the dma engine, it removes the controller out of lock up state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Due to H/W errata, the controller is unable to save the PMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * field fetched from command header before sending the H2D FIS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * When the device returns the PMP port field in the D2H FIS, there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * a mismatch and results in command completion failure. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * workaround is to write the pmp value to PxFBS.DEV field before issuing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * any command to PMP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct xgene_ahci_context *ctx = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 port_fbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Write the pmp value to PxFBS.DEV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * for case of Port Mulitplier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ctx->class[ap->port_no] == ATA_DEV_PMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) port_fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) port_fbs &= ~PORT_FBS_DEV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) port_fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) writel(port_fbs, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (unlikely((ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) (ctx->last_cmd[ap->port_no] == ATA_CMD_PACKET) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (ctx->last_cmd[ap->port_no] == ATA_CMD_SMART)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) xgene_ahci_restart_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rc = ahci_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Save the last command issued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ctx->last_cmd[ap->port_no] = qc->tf.command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void __iomem *diagcsr = ctx->csr_diag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * xgene_ahci_read_id - Read ID data from the specified device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @tf: proposed taskfile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @id: data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * This custom read ID function is required due to the fact that the HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * does not support DEVSLP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static unsigned int xgene_ahci_read_id(struct ata_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct ata_taskfile *tf, u16 *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) err_mask = ata_do_dev_read_id(dev, tf, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (err_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Mask reserved area. Word78 spec of Link Power Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * bit15-8: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * bit7: NCQ autosence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * bit6: Software settings preservation supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * bit5: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * bit4: In-order sata delivery supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * bit3: DIPM requests supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * bit2: DMA Setup FIS Auto-Activate optimization supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * bit1: DMA Setup FIX non-Zero buffer offsets supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * bit0: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void __iomem *mmio = ctx->hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mmio, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) val = readl(mmio + PORTCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(val, mmio + PORTCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) readl(mmio + PORTCFG); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Disable fix rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writel(0x0001fffe, mmio + PORTPHY1CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) readl(mmio + PORTPHY1CFG); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) writel(0x28183219, mmio + PORTPHY2CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) readl(mmio + PORTPHY2CFG); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writel(0x13081008, mmio + PORTPHY3CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) readl(mmio + PORTPHY3CFG); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writel(0x00480815, mmio + PORTPHY4CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) readl(mmio + PORTPHY4CFG); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Set window negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) val = readl(mmio + PORTPHY5CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writel(val, mmio + PORTPHY5CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) readl(mmio + PORTPHY5CFG); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val = readl(mmio + PORTAXICFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) writel(val, mmio + PORTAXICFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) readl(mmio + PORTAXICFG); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Set the watermark threshold of the receive FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) val = readl(mmio + PORTRANSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) val = PORTRANSCFG_RXWM_SET(val, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel(val, mmio + PORTRANSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * xgene_ahci_do_hardreset - Issue the actual COMRESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @link: link to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @online: Return value to indicate if device online
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Due to the limitation of the hardware PHY, a difference set of setting is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * report disparity error and etc. In addition, during COMRESET, there can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * SERR_10B_8B_ERR, the PHY receiver line must be reseted. Also during long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * reboot cycle regression, sometimes the PHY reports link down even if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * device is present because of speed negotiation failure. so need to retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * the COMRESET to get the link up. The following algorithm is followed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * proper configure the hardware PHY during COMRESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Alg Part 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * 1. Start the PHY at Gen3 speed (default setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * 2. Issue the COMRESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * 3. If no link, go to Alg Part 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * 4. If link up, determine if the negotiated speed matches the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * configured speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * 5. If they matched, go to Alg Part 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * 6. If they do not matched and first time, configure the PHY for the linked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * up disk speed and repeat step 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * 7. Go to Alg Part 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Alg Part 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * reported in the register PORT_SCR_ERR, then reset the PHY receiver line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * 2. Go to Alg Part 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Alg Part 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * 1. Check the PORT_SCR_STAT to see whether device presence detected but PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * communication establishment failed and maximum link down attempts are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * less than Max attempts 3 then goto Alg Part 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * 2. Go to Alg Part 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Alg Part 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * 1. Clear any pending from register PORT_SCR_ERR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * and until the underlying PHY supports an method to reset the receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * an warning message will be printed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int xgene_ahci_do_hardreset(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned long deadline, bool *online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct xgene_ahci_context *ctx = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int link_down_retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 val, sstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* clear D2H reception area to properly wait for D2H FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ata_tf_init(link->device, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) tf.command = ATA_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ata_tf_to_fis(&tf, 0, 0, d2h_fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) rc = sata_link_hardreset(link, timing, deadline, online,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (*online) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) val = readl(port_mmio + PORT_SCR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_warn(ctx->dev, "link has error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) sata_scr_read(link, SCR_STATUS, &sstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } while (link_down_retry++ < MAX_LINK_DOWN_RETRY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (sstatus & 0xff) == 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* clear all errors if any pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) val = readl(port_mmio + PORT_SCR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writel(val, port_mmio + PORT_SCR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) bool online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 portcmd_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 portclb_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 portclbhi_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u32 portrxfis_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 portrxfishi_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* As hardreset resets these CSR, save it to restore later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) portcmd_saved = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) portclb_saved = readl(port_mmio + PORT_LST_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) rc = xgene_ahci_do_hardreset(link, deadline, &online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* As controller hardreset clears them, restore them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) writel(portcmd_saved, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) writel(portclb_saved, port_mmio + PORT_LST_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *class = ahci_dev_classify(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void xgene_ahci_host_stop(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * xgene_ahci_pmp_softreset - Issue the softreset to the drives connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * to Port Multiplier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * @link: link to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * @class: Return value to indicate class of device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * Due to H/W errata, the controller is unable to save the PMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * field fetched from command header before sending the H2D FIS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * When the device returns the PMP port field in the D2H FIS, there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * a mismatch and results in command completion failure. The workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * is to write the pmp value to PxFBS.DEV field before issuing any command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * to PMP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int xgene_ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int pmp = sata_srst_pmp(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 port_fbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Set PxFBS.DEV field with pmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) port_fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) port_fbs &= ~PORT_FBS_DEV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) port_fbs |= pmp << PORT_FBS_DEV_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) writel(port_fbs, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) rc = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * xgene_ahci_softreset - Issue the softreset to the drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * @link: link to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @class: Return value to indicate class of device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Due to H/W errata, the controller is unable to save the PMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * field fetched from command header before sending the H2D FIS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * When the device returns the PMP port field in the D2H FIS, there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * a mismatch and results in command completion failure. The workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * is to write the pmp value to PxFBS.DEV field before issuing any command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * to PMP. Here is the algorithm to detect PMP :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * 1. Save the PxFBS value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * 2. Program PxFBS.DEV with pmp value send by framework. Framework sends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * 0xF for both PMP/NON-PMP initially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * 3. Issue softreset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * 4. If signature class is PMP goto 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * 5. restore the original PxFBS and goto 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * 6. return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int xgene_ahci_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int pmp = sata_srst_pmp(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct xgene_ahci_context *ctx = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) void *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 port_fbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 port_fbs_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 retry = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) port_fbs_save = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Set PxFBS.DEV field with pmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) port_fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) port_fbs &= ~PORT_FBS_DEV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) port_fbs |= pmp << PORT_FBS_DEV_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) writel(port_fbs, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) softreset_retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) rc = ahci_do_softreset(link, class, pmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) deadline, ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ctx->class[ap->port_no] = *class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (*class != ATA_DEV_PMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Retry for normal drives without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * setting PxFBS.DEV field with pmp value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (retry--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writel(port_fbs_save, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) goto softreset_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * xgene_ahci_handle_broken_edge_irq - Handle the broken irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * @ata_host: Host that recieved the irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * @irq_masked: HOST_IRQ_STAT value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * For hardware with broken edge trigger latch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * the HOST_IRQ_STAT register misses the edge interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * when clearing of HOST_IRQ_STAT register and hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * reporting the PORT_IRQ_STAT register at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * same clock cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * As such, the algorithm below outlines the workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * 1. Read HOST_IRQ_STAT register and save the state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * 2. Clear the HOST_IRQ_STAT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * 3. Read back the HOST_IRQ_STAT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * 4. If HOST_IRQ_STAT register equals to zero, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * traverse the rest of port's PORT_IRQ_STAT register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * to check if an interrupt is triggered at that point else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * go to step 6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * 5. If PORT_IRQ_STAT register of rest ports is not equal to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * then update the state of HOST_IRQ_STAT saved in step 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * 6. Handle port interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * 7. Exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int xgene_ahci_handle_broken_edge_irq(struct ata_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 irq_masked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) void __iomem *port_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!readl(hpriv->mmio + HOST_IRQ_STAT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (irq_masked & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) port_mmio = ahci_port_base(host->ports[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (readl(port_mmio + PORT_IRQ_STAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) irq_masked |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ahci_handle_port_intr(host, irq_masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 irq_stat, irq_masked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* sigh. 0xffffffff is a valid return from h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) irq_stat = readl(mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!irq_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) irq_masked = irq_stat & hpriv->port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * HOST_IRQ_STAT behaves as edge triggered latch meaning that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * it should be cleared before all the port events are cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) writel(irq_stat, mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) rc = xgene_ahci_handle_broken_edge_irq(host, irq_masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) VPRINTK("EXIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return IRQ_RETVAL(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static struct ata_port_operations xgene_ahci_v1_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .host_stop = xgene_ahci_host_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .hardreset = xgene_ahci_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .read_id = xgene_ahci_read_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .qc_issue = xgene_ahci_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .softreset = xgene_ahci_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .pmp_softreset = xgene_ahci_pmp_softreset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const struct ata_port_info xgene_ahci_v1_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .flags = AHCI_FLAG_COMMON | ATA_FLAG_PMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .port_ops = &xgene_ahci_v1_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static struct ata_port_operations xgene_ahci_v2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .host_stop = xgene_ahci_host_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .hardreset = xgene_ahci_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .read_id = xgene_ahci_read_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const struct ata_port_info xgene_ahci_v2_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .flags = AHCI_FLAG_COMMON | ATA_FLAG_PMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .port_ops = &xgene_ahci_v2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct xgene_ahci_context *ctx = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Remove IP RAM out of shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) rc = xgene_ahci_init_memram(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) xgene_ahci_set_phy_cfg(ctx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* AXI disable Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) writel(0, ctx->csr_core + INTSTATUSMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) INTSTATUSMASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) readl(ctx->csr_axi + INT_SLV_TMOMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* Enable AXI Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Enable coherency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) val = readl(ctx->csr_core + BUSCTLREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) val &= ~0x00000002; /* Enable write coherency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) val &= ~0x00000001; /* Enable read coherency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) writel(val, ctx->csr_core + BUSCTLREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) val = readl(ctx->csr_core + IOFMSTRWAUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) val |= (1 << 3); /* Enable read coherency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) val |= (1 << 9); /* Enable write coherency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) writel(val, ctx->csr_core + IOFMSTRWAUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) val = readl(ctx->csr_core + IOFMSTRWAUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) IOFMSTRWAUX, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Check for optional MUX resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!ctx->csr_mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) val &= ~CFG_SATA_ENET_SELECT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static struct scsi_host_template ahci_platform_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) AHCI_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const struct acpi_device_id xgene_ahci_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) { "APMC0D0D", XGENE_AHCI_V1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) { "APMC0D32", XGENE_AHCI_V2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) MODULE_DEVICE_TABLE(acpi, xgene_ahci_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const struct of_device_id xgene_ahci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {.compatible = "apm,xgene-ahci", .data = (void *) XGENE_AHCI_V1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {.compatible = "apm,xgene-ahci-v2", .data = (void *) XGENE_AHCI_V2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int xgene_ahci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct xgene_ahci_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) const struct of_device_id *of_devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) enum xgene_ahci_version version = XGENE_AHCI_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) const struct ata_port_info *ppi[] = { &xgene_ahci_v1_port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) &xgene_ahci_v2_port_info };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) hpriv = ahci_platform_get_resources(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (IS_ERR(hpriv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return PTR_ERR(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) hpriv->plat_data = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ctx->hpriv = hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Retrieve the IP core resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ctx->csr_core = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (IS_ERR(ctx->csr_core))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return PTR_ERR(ctx->csr_core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Retrieve the IP diagnostic resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ctx->csr_diag = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (IS_ERR(ctx->csr_diag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return PTR_ERR(ctx->csr_diag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Retrieve the IP AXI resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ctx->csr_axi = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (IS_ERR(ctx->csr_axi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return PTR_ERR(ctx->csr_axi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Retrieve the optional IP mux resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) void __iomem *csr = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (IS_ERR(csr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return PTR_ERR(csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ctx->csr_mux = csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) of_devid = of_match_device(xgene_ahci_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (of_devid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (of_devid->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) version = (enum xgene_ahci_version) of_devid->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) const struct acpi_device_id *acpi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct acpi_device_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) acpi_id = acpi_match_device(xgene_ahci_acpi_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!acpi_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_warn(&pdev->dev, "No node entry in ACPI table. Assume version1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) version = XGENE_AHCI_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) } else if (acpi_id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) version = (enum xgene_ahci_version) acpi_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) status = acpi_get_object_info(ACPI_HANDLE(&pdev->dev), &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (ACPI_FAILURE(status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_warn(&pdev->dev, "%s: Error reading device info. Assume version1\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) version = XGENE_AHCI_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (info->valid & ACPI_VALID_CID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) version = XGENE_AHCI_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) hpriv->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* Select ATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if ((rc = xgene_ahci_mux_select(ctx))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_err(dev, "SATA mux selection failed error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (xgene_ahci_is_memram_inited(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_info(dev, "skip clock and PHY initialization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto skip_clk_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Due to errata, HW requires full toggle transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) rc = ahci_platform_enable_clks(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ahci_platform_disable_clks(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) rc = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Configure the host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) xgene_ahci_hw_init(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) skip_clk_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) switch (version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case XGENE_AHCI_V1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) hpriv->flags = AHCI_HFLAG_NO_NCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case XGENE_AHCI_V2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) hpriv->flags |= AHCI_HFLAG_YES_FBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) hpriv->irq_handler = xgene_ahci_irq_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) rc = ahci_platform_init_host(pdev, hpriv, ppi[version - 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) &ahci_platform_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_dbg(dev, "X-Gene SATA host controller initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static struct platform_driver xgene_ahci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .probe = xgene_ahci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .of_match_table = xgene_ahci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .acpi_match_table = ACPI_PTR(xgene_ahci_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) module_platform_driver(xgene_ahci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) MODULE_AUTHOR("Loc Ho <lho@apm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) MODULE_VERSION("0.4");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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