^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/ata/ahci_tegra.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Mikko Perttunen <mperttunen@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <soc/tegra/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRV_NAME "tegra-ahci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SATA_CONFIGURATION_0 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCFG_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define T_SATA0_CFG_1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define T_SATA0_CFG_1_IO_SPACE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define T_SATA0_CFG_1_BUS_MASTER BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define T_SATA0_CFG_1_SERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define T_SATA0_CFG_9 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SATA_FPCI_BAR5 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SATA_FPCI_BAR5_START (0x0040020 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SATA_INTR_MASK 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SATA_INTR_MASK_IP_INT_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define T_SATA0_CFG_35 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define T_SATA0_AHCI_IDP1 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define T_SATA0_AHCI_IDP1_DATA (0x400040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define T_SATA0_CFG_PHY_1 0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define T_SATA0_NVOOB 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define T_SATA_CFG_PHY_0 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define T_SATA0_CFG2NVOOB_2 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define T_SATA0_BKDOOR_CC 0x4a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define T_SATA0_CFG_SATA 0x54c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define T_SATA0_CFG_MISC 0x550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define T_SATA0_INDEX 0x680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define T_SATA0_CHX_PHY_CTRL2 0x69c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define T_SATA0_CHX_PHY_CTRL11 0x6d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* AUX Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SATA_AUX_MISC_CNTL_1_0 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SATA_AUX_RX_STAT_INT_0 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SATA_AUX_SPARE_CFG0_0 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define FUSE_SATA_CALIB 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FUSE_SATA_CALIB_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct sata_pad_calibration {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 gen1_tx_amp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 gen1_tx_peak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 gen2_tx_amp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 gen2_tx_peak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct sata_pad_calibration tegra124_pad_calibration[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x18, 0x04, 0x18, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x0e, 0x04, 0x14, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x0e, 0x07, 0x1a, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x14, 0x0e, 0x1a, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct tegra_ahci_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int (*init)(struct ahci_host_priv *hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct tegra_ahci_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const char *const *supply_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 num_supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) bool supports_devslp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const struct tegra_ahci_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct tegra_ahci_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void __iomem *sata_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void __iomem *sata_aux_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct reset_control *sata_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct reset_control *sata_oob_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct reset_control *sata_cold_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Needs special handling, cannot use ahci_platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct clk *sata_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct regulator_bulk_data *supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const struct tegra_ahci_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct tegra_ahci_priv *tegra = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct tegra_ahci_priv *tegra = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct sata_pad_calibration calib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Pad calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) val = readl(tegra->sata_regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel(val, tegra->sata_regs + SCFG_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) T_SATA0_CHX_PHY_CTRL1_GEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) val = readl(tegra->sata_regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel(val, tegra->sata_regs + SCFG_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) T_SATA0_CHX_PHY_CTRL1_GEN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct tegra_ahci_priv *tegra = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = regulator_bulk_enable(tegra->soc->num_supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tegra->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tegra->sata_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) tegra->sata_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto disable_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) reset_control_assert(tegra->sata_oob_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) reset_control_assert(tegra->sata_cold_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) goto disable_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) reset_control_deassert(tegra->sata_cold_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) reset_control_deassert(tegra->sata_oob_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) disable_power:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clk_disable_unprepare(tegra->sata_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) disable_regulators:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct tegra_ahci_priv *tegra = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) reset_control_assert(tegra->sata_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) reset_control_assert(tegra->sata_oob_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) reset_control_assert(tegra->sata_cold_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) clk_disable_unprepare(tegra->sata_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct tegra_ahci_priv *tegra = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = tegra_ahci_power_on(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(&tegra->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "failed to power on AHCI controller: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Program the following SATA IPFS registers to allow SW accesses to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * SATA's MMIO register range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Program the following SATA IPFS register to enable the SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val |= SATA_CONFIGURATION_0_EN_FPCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Electrical settings for better link stability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) val |= (T_SATA0_NVOOB_COMMA_CNT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (tegra->soc->ops && tegra->soc->ops->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tegra->soc->ops->init(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Program the following SATA configuration registers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * initialize SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) val = T_SATA0_CFG_9_BASE_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Program Class Code and Programming interface for SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) val &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) T_SATA0_BKDOOR_CC_PROG_IF_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Enabling LPM capabilities through Backdoor Programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* SATA Second Level Clock Gating configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * IDDQ Signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) val |= T_SATA0_CFG_35_IDP_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) val = T_SATA0_AHCI_IDP1_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Enabling IPFS Clock Gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) tegra_ahci_handle_quirks(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Unmask SATA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) val = readl(tegra->sata_regs + SATA_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val |= SATA_INTR_MASK_IP_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) writel(val, tegra->sata_regs + SATA_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tegra_ahci_power_off(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void tegra_ahci_host_stop(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) tegra_ahci_controller_deinit(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct ata_port_operations ahci_tegra_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .host_stop = tegra_ahci_host_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct ata_port_info ahci_tegra_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .port_ops = &ahci_tegra_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const char *const tegra124_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "avdd", "hvdd", "vddio", "target-5v", "target-12v"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct tegra_ahci_ops tegra124_ahci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .init = tegra124_ahci_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct tegra_ahci_soc tegra124_ahci_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .supply_names = tegra124_supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .num_supplies = ARRAY_SIZE(tegra124_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .supports_devslp = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .ops = &tegra124_ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct tegra_ahci_soc tegra210_ahci_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .supports_devslp = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct of_device_id tegra_ahci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .compatible = "nvidia,tegra124-ahci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .data = &tegra124_ahci_soc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .compatible = "nvidia,tegra210-ahci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .data = &tegra210_ahci_soc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static struct scsi_host_template ahci_platform_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) AHCI_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int tegra_ahci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct tegra_ahci_priv *tegra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) hpriv = ahci_platform_get_resources(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (IS_ERR(hpriv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return PTR_ERR(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) hpriv->plat_data = tegra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tegra->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tegra->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (IS_ERR(tegra->sata_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return PTR_ERR(tegra->sata_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * AUX registers is optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (IS_ERR(tegra->sata_aux_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return PTR_ERR(tegra->sata_aux_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (IS_ERR(tegra->sata_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_err(&pdev->dev, "Failed to get sata reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return PTR_ERR(tegra->sata_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (IS_ERR(tegra->sata_oob_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return PTR_ERR(tegra->sata_oob_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (IS_ERR(tegra->sata_cold_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return PTR_ERR(tegra->sata_cold_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (IS_ERR(tegra->sata_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_err(&pdev->dev, "Failed to get sata clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return PTR_ERR(tegra->sata_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) tegra->supplies = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) tegra->soc->num_supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) sizeof(*tegra->supplies), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!tegra->supplies)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) regulator_bulk_set_supply_names(tegra->supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) tegra->soc->supply_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) tegra->soc->num_supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = devm_regulator_bulk_get(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) tegra->soc->num_supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) tegra->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_err(&pdev->dev, "Failed to get regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = tegra_ahci_controller_init(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) &ahci_platform_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) goto deinit_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) deinit_controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) tegra_ahci_controller_deinit(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static struct platform_driver tegra_ahci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .probe = tegra_ahci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .of_match_table = tegra_ahci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* LP0 suspend support not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) module_platform_driver(tegra_ahci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MODULE_DESCRIPTION("Tegra AHCI SATA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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