^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Allwinner sunxi AHCI SATA platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Daniel Wang <danielwang@allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRV_NAME "ahci-sunxi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Insmod parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static bool enable_pmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) module_param(enable_pmp, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_PARM_DESC(enable_pmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "Enable support for sata port multipliers, only use if you use a pmp!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AHCI_BISTAFR 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AHCI_BISTCR 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AHCI_BISTFCTR 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AHCI_BISTSR 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AHCI_BISTDECR 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AHCI_DIAGNR0 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AHCI_DIAGNR1 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AHCI_OOBR 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AHCI_PHYCS0R 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AHCI_PHYCS1R 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AHCI_PHYCS2R 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AHCI_TIMER1MS 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AHCI_GPARAM1R 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AHCI_GPARAM2R 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AHCI_PPARAMR 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AHCI_TESTR 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AHCI_VERSIONR 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AHCI_IDR 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AHCI_RWCR 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AHCI_P0DMACR 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AHCI_P0PHYCR 0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AHCI_P0PHYSR 0x017c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) reg_val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg_val &= ~(clr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writel(reg_val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void sunxi_setbits(void __iomem *reg, u32 set_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg_val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg_val |= set_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(reg_val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg_val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg_val &= ~(clr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reg_val |= set_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel(reg_val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return (readl(reg) >> shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* This magic is from the original code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel(0, reg_base + AHCI_RWCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (0x7 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (0x5 << 24) | BIT(23) | BIT(18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (0x7 << 20), (0x3 << 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (0x1f << 5), (0x19 << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) timeout = 250; /* Power up takes aprox 50 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (reg_val == 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (--timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_err(dev, "PHY power up failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) timeout = 100; /* Calibration takes aprox 10 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (reg_val == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (--timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev_err(dev, "PHY calibration failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) msleep(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(0x7, reg_base + AHCI_RWCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void ahci_sunxi_start_engine(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Setup DMA before DMA start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * NOTE: A similar SoC with SATA/AHCI by Texas Instruments documents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * this Vendor Specific Port (P0DMACR, aka PxDMACR) in its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * User's Guide document (TMS320C674x/OMAP-L1x Processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Serial ATA (SATA) Controller, Literature Number: SPRUGJ8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * p.68, https://www.ti.com/lit/ug/sprugj8c/sprugj8c.pdf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * as equivalent to the following struct:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * struct AHCI_P0DMACR_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * unsigned TXTS : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * unsigned RXTS : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * unsigned TXABL : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * unsigned RXABL : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * unsigned Reserved : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * TXTS: Transmit Transaction Size (TX_TRANSACTION_SIZE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * This field defines the DMA transaction size in DWORDs for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * transmit (system bus read, device write) operation. [...]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * RXTS: Receive Transaction Size (RX_TRANSACTION_SIZE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * This field defines the Port DMA transaction size in DWORDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * for receive (system bus write, device read) operation. [...]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * TXABL: Transmit Burst Limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * This field allows software to limit the VBUSP master read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * burst size. [...]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * RXABL: Receive Burst Limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Allows software to limit the VBUSP master write burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * size. [...]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Reserved: Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * NOTE: According to the above document, the following alternative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * to the code below could perhaps be a better option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * (or preparation) for possible further improvements later:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * 0x00000033);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 0x00004433);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct ata_port_info ahci_sunxi_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ | ATA_FLAG_NO_DIPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .port_ops = &ahci_platform_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct scsi_host_template ahci_platform_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) AHCI_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int ahci_sunxi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) hpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (IS_ERR(hpriv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return PTR_ERR(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) hpriv->start_engine = ahci_sunxi_start_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rc = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) AHCI_HFLAG_YES_NCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * The sunxi sata controller seems to be unable to successfully do a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * soft reset if no pmp is attached, so disable pmp use unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * requested, otherwise directly attached disks do not work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!enable_pmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) hpriv->flags |= AHCI_HFLAG_NO_PMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) &ahci_platform_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int ahci_sunxi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) rc = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) rc = ahci_platform_resume_host(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ahci_sunxi_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct of_device_id ahci_sunxi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { .compatible = "allwinner,sun4i-a10-ahci", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { .compatible = "allwinner,sun8i-r40-ahci", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct platform_driver ahci_sunxi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .probe = ahci_sunxi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .of_match_table = ahci_sunxi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .pm = &ahci_sunxi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) module_platform_driver(ahci_sunxi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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