^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale QorIQ AHCI SATA platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2015 Freescale, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Tang Yuantian <Yuantian.Tang@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRV_NAME "ahci-qoriq"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* port register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PORT_PHY1 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PORT_PHY2 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PORT_PHY3 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PORT_PHY4 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PORT_PHY5 0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PORT_AXICC 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PORT_TRANS 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* port register default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AHCI_PORT_PHY_1_CFG 0xa003fffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AHCI_PORT_PHY2_CFG 0x28184d1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AHCI_PORT_PHY3_CFG 0x0e081509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AHCI_PORT_TRANS_CFG 0x08000029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AHCI_PORT_AXICC_CFG 0x3fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* for ls1021a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LS1021A_PORT_PHY2 0x28183414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LS1021A_PORT_PHY3 0x0e080e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LS1021A_PORT_PHY4 0x064a080b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LS1021A_PORT_PHY5 0x2aa86470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LS1021A_AXICC_ADDR 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SATA_ECC_DISABLE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ECC_DIS_ARMV8_CH2 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ECC_DIS_LS1088A 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum ahci_qoriq_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) AHCI_LS1021A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) AHCI_LS1028A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) AHCI_LS1043A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) AHCI_LS2080A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) AHCI_LS1046A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) AHCI_LS1088A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) AHCI_LS2088A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) AHCI_LX2160A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct ahci_qoriq_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct ccsr_ahci *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) enum ahci_qoriq_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *ecc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bool is_dmacoherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static bool ecc_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct of_device_id ahci_qoriq_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void __iomem *port_mmio = ahci_port_base(link->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 px_cmd, px_is, px_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bool online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * A-009042: The device detection initialization sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * mistakenly resets some registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Workaround for this is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * The software should read and store PxCMD and PxIS values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * before issuing the device detection initialization sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * After the sequence is complete, software should restore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * PxCMD and PxIS with the stored values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ls1021a_workaround) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) px_cmd = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) px_is = readl(port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* clear D2H reception area to properly wait for D2H FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ata_tf_init(link->device, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) tf.command = ATA_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ata_tf_to_fis(&tf, 0, 0, d2h_fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) rc = sata_link_hardreset(link, timing, deadline, &online,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* restore the PxCMD and PxIS on ls1021 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ls1021a_workaround) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) px_val = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (px_val != px_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writel(px_cmd, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) px_val = readl(port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (px_val != px_is)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(px_is, port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *class = ahci_dev_classify(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct ata_port_operations ahci_qoriq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .hardreset = ahci_qoriq_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct ata_port_info ahci_qoriq_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .port_ops = &ahci_qoriq_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct scsi_host_template ahci_qoriq_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) AHCI_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void __iomem *reg_base = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) switch (qpriv->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case AHCI_LS1021A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!(qpriv->ecc_addr || ecc_initialized))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else if (qpriv->ecc_addr && !ecc_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (qpriv->is_dmacoherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(AHCI_PORT_AXICC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) reg_base + LS1021A_AXICC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case AHCI_LS1043A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!(qpriv->ecc_addr || ecc_initialized))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) else if (qpriv->ecc_addr && !ecc_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel(readl(qpriv->ecc_addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ECC_DIS_ARMV8_CH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) qpriv->ecc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (qpriv->is_dmacoherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case AHCI_LS2080A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (qpriv->is_dmacoherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case AHCI_LS1046A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!(qpriv->ecc_addr || ecc_initialized))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else if (qpriv->ecc_addr && !ecc_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel(readl(qpriv->ecc_addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ECC_DIS_ARMV8_CH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) qpriv->ecc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (qpriv->is_dmacoherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case AHCI_LS1028A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case AHCI_LS1088A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case AHCI_LX2160A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!(qpriv->ecc_addr || ecc_initialized))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) else if (qpriv->ecc_addr && !ecc_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writel(readl(qpriv->ecc_addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ECC_DIS_LS1088A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) qpriv->ecc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (qpriv->is_dmacoherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case AHCI_LS2088A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (qpriv->is_dmacoherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ecc_initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int ahci_qoriq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) const struct acpi_device_id *acpi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct ahci_qoriq_priv *qoriq_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) hpriv = ahci_platform_get_resources(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (IS_ERR(hpriv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return PTR_ERR(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) of_id = of_match_node(ahci_qoriq_of_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!(of_id || acpi_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!qoriq_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (unlikely(!ecc_initialized)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) res = platform_get_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "sata-ecc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) qoriq_priv->ecc_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (IS_ERR(qoriq_priv->ecc_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return PTR_ERR(qoriq_priv->ecc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) qoriq_priv->is_dmacoherent = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) rc = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) hpriv->plat_data = qoriq_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) rc = ahci_qoriq_phy_init(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) &ahci_qoriq_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int ahci_qoriq_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rc = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) rc = ahci_qoriq_phy_init(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rc = ahci_platform_resume_host(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* We resumed so update PM runtime state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ahci_qoriq_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct platform_driver ahci_qoriq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .probe = ahci_qoriq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .of_match_table = ahci_qoriq_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .acpi_match_table = ahci_qoriq_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .pm = &ahci_qoriq_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) module_platform_driver(ahci_qoriq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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