Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * AHCI glue platform driver for Marvell EBU SOCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2014 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Marcin Wojtas <mw@semihalf.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DRV_NAME "ahci-mvebu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AHCI_VENDOR_SPECIFIC_0_ADDR  0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AHCI_VENDOR_SPECIFIC_0_DATA  0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AHCI_WINDOW_CTRL(win)	(0x60 + ((win) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AHCI_WINDOW_BASE(win)	(0x64 + ((win) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AHCI_WINDOW_SIZE(win)	(0x68 + ((win) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct ahci_mvebu_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	int (*plat_config)(struct ahci_host_priv *hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static void ahci_mvebu_mbus_config(struct ahci_host_priv *hpriv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 				   const struct mbus_dram_target_info *dram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	for (i = 0; i < dram->num_cs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		const struct mbus_dram_window *cs = dram->cs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		writel((cs->mbus_attr << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		       (dram->mbus_dram_target_id << 4) | 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		       hpriv->mmio + AHCI_WINDOW_CTRL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		writel(((cs->size - 1) & 0xffff0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		       hpriv->mmio + AHCI_WINDOW_SIZE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void ahci_mvebu_regret_option(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * Enable the regret bit to allow the SATA unit to regret a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * request that didn't receive an acknowlegde and avoid a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 * deadlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int ahci_mvebu_armada_380_config(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	const struct mbus_dram_target_info *dram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	dram = mv_mbus_dram_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	if (dram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		ahci_mvebu_mbus_config(hpriv, dram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ahci_mvebu_regret_option(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int ahci_mvebu_armada_3700_config(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	writel(0, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	reg = readl(hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	reg |= BIT(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	writel(reg, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * ahci_mvebu_stop_engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * @ap:	Target ata port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * Errata Ref#226 - SATA Disk HOT swap issue when connected through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * Port Multiplier in FIS-based Switching mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * To avoid the issue, according to design, the bits[11:8, 0] of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * register PxFBS are cleared when Port Command and Status (0x18) bit[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * changes its value from 1 to 0, i.e. falling edge of Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * Command and Status bit[0] sends PULSE that resets PxFBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * bits[11:8; 0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * This function is used to override function of "ahci_stop_engine"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * from libahci.c by adding the mvebu work around(WA) to save PxFBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * value before the PxCMD ST write of 0, then restore PxFBS value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * Return: 0 on success; Error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int ahci_mvebu_stop_engine(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u32 tmp, port_fbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	tmp = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* check if the HBA is idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* save the port PxFBS register for later restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	port_fbs = readl(port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* setting HBA to idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	tmp &= ~PORT_CMD_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	writel(tmp, port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 * bit #15 PxCMD signal doesn't clear PxFBS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * restore the PxFBS register right after clearing the PxCMD ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * no need to wait for the PxCMD bit #15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	writel(port_fbs, port_mmio + PORT_FBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* wait for engine to stop. This could be as long as 500 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (tmp & PORT_CMD_LIST_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int ahci_mvebu_suspend(struct platform_device *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return ahci_platform_suspend_host(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int ahci_mvebu_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct ata_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	const struct ahci_mvebu_plat_data *pdata = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	pdata->plat_config(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return ahci_platform_resume_host(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ahci_mvebu_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ahci_mvebu_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct ata_port_info ahci_mvebu_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.flags	   = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.pio_mask  = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.port_ops  = &ahci_platform_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct scsi_host_template ahci_platform_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	AHCI_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int ahci_mvebu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	const struct ahci_mvebu_plat_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	pdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	hpriv = ahci_platform_get_resources(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (IS_ERR(hpriv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return PTR_ERR(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	hpriv->flags |= pdata->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	hpriv->plat_data = (void *)pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	rc = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	hpriv->stop_engine = ahci_mvebu_stop_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	rc = pdata->plat_config(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 				     &ahci_platform_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct ahci_mvebu_plat_data ahci_mvebu_armada_380_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.plat_config = ahci_mvebu_armada_380_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.plat_config = ahci_mvebu_armada_3700_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.flags = AHCI_HFLAG_SUSPEND_PHYS | AHCI_HFLAG_IGN_NOTSUPP_POWER_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct of_device_id ahci_mvebu_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.compatible = "marvell,armada-380-ahci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.data = &ahci_mvebu_armada_380_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.compatible = "marvell,armada-3700-ahci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.data = &ahci_mvebu_armada_3700_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct platform_driver ahci_mvebu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.probe = ahci_mvebu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.suspend = ahci_mvebu_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.resume = ahci_mvebu_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.of_match_table = ahci_mvebu_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) module_platform_driver(ahci_mvebu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MODULE_DESCRIPTION("Marvell EBU AHCI SATA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Marcin Wojtas <mw@semihalf.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_ALIAS("platform:ahci_mvebu");