^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MediaTek AHCI SATA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DRV_NAME "ahci-mtk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SYS_CFG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SYS_CFG_SATA_MSK GENMASK(31, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SYS_CFG_SATA_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct mtk_ahci_plat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct regmap *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct reset_control *axi_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct reset_control *sw_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct reset_control *reg_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const struct ata_port_info ahci_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .port_ops = &ahci_platform_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct scsi_host_template ahci_platform_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) AHCI_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct mtk_ahci_plat *plat = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* reset AXI bus and PHY part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (PTR_ERR(plat->axi_rst) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return PTR_ERR(plat->axi_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) plat->sw_rst = devm_reset_control_get_optional_exclusive(dev, "sw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (PTR_ERR(plat->sw_rst) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return PTR_ERR(plat->sw_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) plat->reg_rst = devm_reset_control_get_optional_exclusive(dev, "reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (PTR_ERR(plat->reg_rst) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return PTR_ERR(plat->reg_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) err = reset_control_assert(plat->axi_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dev_err(dev, "failed to assert AXI bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) err = reset_control_assert(plat->sw_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dev_err(dev, "failed to assert PHY digital part\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) err = reset_control_assert(plat->reg_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dev_err(dev, "failed to assert PHY register part\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) err = reset_control_deassert(plat->reg_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_err(dev, "failed to deassert PHY register part\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) err = reset_control_deassert(plat->sw_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_err(dev, "failed to deassert PHY digital part\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) err = reset_control_deassert(plat->axi_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev_err(dev, "failed to deassert AXI bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mtk_ahci_plat *plat = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* enable SATA function if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (of_find_property(np, "mediatek,phy-mode", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) plat->mode = syscon_regmap_lookup_by_phandle(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) np, "mediatek,phy-mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (IS_ERR(plat->mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_err(dev, "missing phy-mode phandle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return PTR_ERR(plat->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_update_bits(plat->mode, SYS_CFG, SYS_CFG_SATA_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SYS_CFG_SATA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int mtk_ahci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct mtk_ahci_plat *plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!plat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) hpriv = ahci_platform_get_resources(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (IS_ERR(hpriv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return PTR_ERR(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) hpriv->plat_data = plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) err = mtk_ahci_parse_property(hpriv, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) err = mtk_ahci_platform_resets(hpriv, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) err = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) err = ahci_platform_init_host(pdev, hpriv, &ahci_port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) &ahci_platform_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ahci_platform_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct of_device_id ahci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .compatible = "mediatek,mtk-ahci", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MODULE_DEVICE_TABLE(of, ahci_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct platform_driver mtk_ahci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .probe = mtk_ahci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .of_match_table = ahci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .pm = &ahci_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) module_platform_driver(mtk_ahci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MODULE_DESCRIPTION("MediaTek SATA AHCI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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