^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * copyright (c) 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Freescale IMX AHCI SATA platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRV_NAME "ahci-imx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Timer 1-ms Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) IMX_TIMER1MS = 0x00e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Port0 PHY Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) IMX_P0PHYCR = 0x0178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) IMX_P0PHYCR_CR_READ = 1 << 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) IMX_P0PHYCR_CR_WRITE = 1 << 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Port0 PHY Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) IMX_P0PHYSR = 0x017c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) IMX_P0PHYSR_CR_ACK = 1 << 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Lane0 Output Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) IMX_LANE0_OUT_STAT = 0x2003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Clock Reset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) IMX_CLOCK_RESET = 0x7f3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) IMX_CLOCK_RESET_RESET = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* IMX8QM HSIO AHCI definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) IMX8QM_LPCG_PHYX2_OFFSET = 0x00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) IMX8QM_CSR_PHYX2_OFFSET = 0x90000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) IMX8QM_CSR_PHYX1_OFFSET = 0xa0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) IMX8QM_CSR_PHYX_STTS0_OFFSET = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) IMX8QM_CSR_PCIEA_OFFSET = 0xb0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) IMX8QM_CSR_PCIEB_OFFSET = 0xc0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) IMX8QM_CSR_SATA_OFFSET = 0xd0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) IMX8QM_CSR_PCIE_CTRL2_OFFSET = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) IMX8QM_CSR_MISC_OFFSET = 0xe0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) IMX8QM_LPCG_PHYX2_PCLK0_MASK = (0x3 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) IMX8QM_LPCG_PHYX2_PCLK1_MASK = (0x3 << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) IMX8QM_PHY_APB_RSTN_0 = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) IMX8QM_PHY_MODE_SATA = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) IMX8QM_PHY_MODE_MASK = (0xf << 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) IMX8QM_PHY_PIPE_RSTN_0 = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0 = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) IMX8QM_PHY_PIPE_RSTN_1 = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1 = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) IMX8QM_STTS0_LANE0_TX_PLL_LOCK = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) IMX8QM_MISC_IOB_RXENA = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) IMX8QM_MISC_IOB_TXENA = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) IMX8QM_MISC_PHYX1_EPCS_SEL = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) IMX8QM_SATA_CTRL_RESET_N = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) IMX8QM_SATA_CTRL_EPCS_PHYRESET_N = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) IMX8QM_CTRL_BUTTON_RST_N = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) IMX8QM_CTRL_POWER_UP_RST_N = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) IMX8QM_CTRL_LTSSM_ENABLE = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum ahci_imx_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) AHCI_IMX53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) AHCI_IMX6Q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) AHCI_IMX6QP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) AHCI_IMX8QM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct imx_ahci_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct platform_device *ahci_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum ahci_imx_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk *sata_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk *sata_ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct clk *ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct clk *epcs_tx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk *epcs_rx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk *phy_apbclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct clk *phy_pclk0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk *phy_pclk1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void __iomem *phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct gpio_desc *clkreq_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bool no_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bool first_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 phy_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 imped_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int ahci_imx_hotplug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void ahci_imx_host_stop(struct ata_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 crval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 srval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Assert or deassert the bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) crval = readl(mmio + IMX_P0PHYCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) crval |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) crval &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel(crval, mmio + IMX_P0PHYCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Wait for the cr_ack signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) srval = readl(mmio + IMX_P0PHYSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return timeout ? 0 : -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 crval = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Supply the address on cr_data_in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(crval, mmio + IMX_P0PHYCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Assert the cr_cap_addr signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Deassert cr_cap_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int imx_phy_reg_write(u16 val, void __iomem *mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 crval = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Supply the data on cr_data_in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(crval, mmio + IMX_P0PHYCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Assert the cr_cap_data signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Deassert cr_cap_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (val & IMX_CLOCK_RESET_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * In case we're resetting the phy, it's unable to acknowledge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * so we return immediately here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) crval |= IMX_P0PHYCR_CR_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) writel(crval, mmio + IMX_P0PHYCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Assert the cr_write signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Deassert cr_write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Assert the cr_read signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Capture the data from cr_data_out[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Deassert cr_read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct imx_ahci_priv *imxpriv = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (imxpriv->type == AHCI_IMX6QP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* 6qp adds the sata reset mechanism, use it for 6qp sata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) IMX6Q_GPR5_SATA_SW_PD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) IMX6Q_GPR5_SATA_SW_RST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IMX6Q_GPR5_SATA_SW_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) IMX6Q_GPR5_SATA_SW_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Wait for PHY RX_PLL to be stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = imx_phy_reg_read(&val, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return timeout ? 0 : -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* SATA PHY Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u16 adc_out_reg, read_sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 index, read_attempt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const u32 attempt_limit = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) imx_phy_reg_write(rtune_ctl_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* two dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) read_attempt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) adc_out_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) while (index < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) imx_phy_reg_read(&adc_out_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* check if valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (adc_out_reg & 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) read_attempt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (read_attempt > attempt_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(dev, "Read REG more than %d times!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) attempt_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) read_attempt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) read_sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) while (index < 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) imx_phy_reg_read(&adc_out_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (adc_out_reg & 0x400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) read_sum = read_sum + (adc_out_reg & 0x3FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) read_attempt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (read_attempt > attempt_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(dev, "Read REG more than %d times!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) attempt_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Use the U32 to make 1000 precision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return (read_sum * 1000) / 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* SATA AHCI temperature monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int sata_ahci_read_temperature(void *dev, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 str1, str2, str3, str4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int m1, m2, a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct ahci_host_priv *hpriv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* check rd-wr to reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) read_sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) imx_phy_reg_write(read_sum, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) imx_phy_reg_read(&read_sum, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if ((read_sum & 0xffff) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) imx_phy_reg_write(0x5A5A, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) imx_phy_reg_read(&read_sum, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if ((read_sum & 0xffff) != 0x5A5A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) imx_phy_reg_write(0x1234, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) imx_phy_reg_read(&read_sum, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if ((read_sum & 0xffff) != 0x1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* start temperature test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) imx_phy_reg_read(&mpll_test_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) imx_phy_reg_read(&rtune_ctl_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) imx_phy_reg_read(&dac_ctl_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* mpll_tst.meas_iv ([12:2]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) str1 = (mpll_test_reg >> 2) & 0x7FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* rtune_ctl.mode ([1:0]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) str2 = (rtune_ctl_reg) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* dac_ctl.dac_mode ([14:12]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) str3 = (dac_ctl_reg >> 12) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* rtune_ctl.sel_atbp ([4]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) str4 = (rtune_ctl_reg >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Calculate the m1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* mpll_tst.meas_iv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* rtune_ctl.mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* dac_ctl.dac_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* rtune_ctl.sel_atbp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) imx_phy_reg_write(mpll_test_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) imx_phy_reg_write(dac_ctl_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) m1 = read_adc_sum(dev, rtune_ctl_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Calculate the m2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* rtune_ctl.sel_atbp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) m2 = read_adc_sum(dev, rtune_ctl_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* restore the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* mpll_tst.meas_iv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* rtune_ctl.mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* dac_ctl.dac_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* rtune_ctl.sel_atbp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) imx_phy_reg_write(mpll_test_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) imx_phy_reg_write(dac_ctl_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) imx_phy_reg_write(rtune_ctl_reg, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Compute temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!(m2 / 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) m2 = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) a = (m2 - m1) / (m2/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) *temp = ((-559) * a * a) / 1000 + (1379) * a + (-458000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static ssize_t sata_ahci_show_temp(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) err = sata_ahci_read_temperature(dev, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return sprintf(buf, "%u\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct thermal_zone_of_device_ops fsl_sata_ahci_of_thermal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .get_temp = sata_ahci_read_temperature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, sata_ahci_show_temp, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct attribute *fsl_sata_ahci_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &sensor_dev_attr_temp1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ATTRIBUTE_GROUPS(fsl_sata_ahci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int imx8_sata_enable(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct imx_ahci_priv *imxpriv = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct device *dev = &imxpriv->ahci_pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* configure the hsio for sata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = clk_prepare_enable(imxpriv->phy_pclk0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev_err(dev, "can't enable phy_pclk0.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = clk_prepare_enable(imxpriv->phy_pclk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_err(dev, "can't enable phy_pclk1.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) goto disable_phy_pclk0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(dev, "can't enable epcs_tx_clk.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) goto disable_phy_pclk1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(dev, "can't enable epcs_rx_clk.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto disable_epcs_tx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = clk_prepare_enable(imxpriv->phy_apbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_err(dev, "can't enable phy_apbclk.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) goto disable_epcs_rx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Configure PHYx2 PIPE_RSTN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* The link of the PCIEA of HSIO is down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) IMX8QM_CSR_PHYX2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) IMX8QM_PHY_PIPE_RSTN_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) IMX8QM_PHY_PIPE_RSTN_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) IMX8QM_CSR_PCIE_CTRL2_OFFSET, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* The link of the PCIEB of HSIO is down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) IMX8QM_CSR_PHYX2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) IMX8QM_PHY_PIPE_RSTN_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) IMX8QM_PHY_PIPE_RSTN_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* The links of both PCIA and PCIEB of HSIO are down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) IMX8QM_LPCG_PHYX2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) IMX8QM_LPCG_PHYX2_PCLK0_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) IMX8QM_LPCG_PHYX2_PCLK1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* set PWR_RST and BT_RST of csr_pciea */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) IMX8QM_CTRL_BUTTON_RST_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) IMX8QM_CTRL_BUTTON_RST_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) IMX8QM_CTRL_POWER_UP_RST_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) IMX8QM_CTRL_POWER_UP_RST_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* PHYX1_MODE to SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) IMX8QM_CSR_PHYX1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) IMX8QM_PHY_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) IMX8QM_PHY_MODE_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * BIT0 RXENA 1, BIT1 TXENA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * BIT12 PHY_X1_EPCS_SEL 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) IMX8QM_CSR_MISC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) IMX8QM_MISC_IOB_RXENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) IMX8QM_MISC_IOB_RXENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) IMX8QM_CSR_MISC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) IMX8QM_MISC_IOB_TXENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) IMX8QM_CSR_MISC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) IMX8QM_MISC_PHYX1_EPCS_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) IMX8QM_MISC_PHYX1_EPCS_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * It is possible, for PCIe and SATA are sharing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * the same clock source, HPLL or external oscillator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * When PCIe is in low power modes (L1.X or L2 etc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * the clock source can be turned off. In this case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * if this clock source is required to be toggling by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * SATA, then SATA functions will be abnormal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Set the override here to avoid it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) IMX8QM_CSR_MISC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* clear PHY RST, then set it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) IMX8QM_CSR_SATA_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) IMX8QM_CSR_SATA_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) IMX8QM_CSR_SATA_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) IMX8QM_SATA_CTRL_RESET_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) IMX8QM_SATA_CTRL_RESET_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) IMX8QM_CSR_SATA_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) IMX8QM_SATA_CTRL_RESET_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) IMX8QM_CSR_SATA_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) IMX8QM_SATA_CTRL_RESET_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) IMX8QM_SATA_CTRL_RESET_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* APB reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) regmap_update_bits(imxpriv->gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) IMX8QM_CSR_PHYX1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) IMX8QM_PHY_APB_RSTN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) IMX8QM_PHY_APB_RSTN_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) reg = IMX8QM_CSR_PHYX1_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) IMX8QM_CSR_PHYX_STTS0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) regmap_read(imxpriv->gpr, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(dev, "TX PLL of the PHY is not locked\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) writeb(imxpriv->imped_ratio, imxpriv->phy_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) writeb(imxpriv->imped_ratio, imxpriv->phy_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) reg = readb(imxpriv->phy_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (unlikely(reg != imxpriv->imped_ratio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_info(dev, "Can't set PHY RX impedance ratio.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) reg = readb(imxpriv->phy_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (unlikely(reg != imxpriv->imped_ratio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_info(dev, "Can't set PHY TX impedance ratio.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) usleep_range(50, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * To reduce the power consumption, gate off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * the PHY clks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) clk_disable_unprepare(imxpriv->phy_apbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) clk_disable_unprepare(imxpriv->phy_pclk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) clk_disable_unprepare(imxpriv->phy_pclk0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) clk_disable_unprepare(imxpriv->phy_apbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) disable_epcs_rx_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) clk_disable_unprepare(imxpriv->epcs_rx_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) disable_epcs_tx_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) clk_disable_unprepare(imxpriv->epcs_tx_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) disable_phy_pclk1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) clk_disable_unprepare(imxpriv->phy_pclk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) disable_phy_pclk0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) clk_disable_unprepare(imxpriv->phy_pclk0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int imx_sata_enable(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct imx_ahci_priv *imxpriv = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct device *dev = &imxpriv->ahci_pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (imxpriv->no_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = ahci_platform_enable_regulators(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = clk_prepare_enable(imxpriv->sata_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto disable_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * set PHY Paremeters, two steps to configure the GPR13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * one write for rest of parameters, mask of first write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * is 0x07ffffff, and the other one write for setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * the mpll_clk_en.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) IMX6Q_GPR13_SATA_SPD_MODE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) IMX6Q_GPR13_SATA_MPLL_SS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) IMX6Q_GPR13_SATA_TX_BOOST_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) IMX6Q_GPR13_SATA_TX_LVL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) IMX6Q_GPR13_SATA_MPLL_CLK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) IMX6Q_GPR13_SATA_TX_EDGE_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) imxpriv->phy_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) IMX6Q_GPR13_SATA_MPLL_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) IMX6Q_GPR13_SATA_MPLL_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = imx_sata_phy_reset(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_err(dev, "failed to reset phy: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else if (imxpriv->type == AHCI_IMX8QM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = imx8_sata_enable(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) clk_disable_unprepare(imxpriv->sata_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) disable_regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ahci_platform_disable_regulators(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static void imx_sata_disable(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct imx_ahci_priv *imxpriv = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (imxpriv->no_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) switch (imxpriv->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) case AHCI_IMX6QP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) IMX6Q_GPR5_SATA_SW_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) IMX6Q_GPR5_SATA_SW_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) IMX6Q_GPR13_SATA_MPLL_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case AHCI_IMX6Q:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) IMX6Q_GPR13_SATA_MPLL_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) case AHCI_IMX8QM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) clk_disable_unprepare(imxpriv->epcs_rx_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) clk_disable_unprepare(imxpriv->epcs_tx_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clk_disable_unprepare(imxpriv->sata_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ahci_platform_disable_regulators(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static void ahci_imx_error_handler(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct ata_host *host = dev_get_drvdata(ap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct imx_ahci_priv *imxpriv = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ahci_error_handler(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!(imxpriv->first_time) || ahci_imx_hotplug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) imxpriv->first_time = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ata_for_each_dev(dev, &ap->link, ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * Disable link to save power. An imx ahci port can't be recovered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * without full reset once the pddq mode is enabled making it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * impossible to use as part of libata LPM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) reg_val = readl(mmio + IMX_P0PHYCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) imx_sata_disable(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) imxpriv->no_device = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_info(ap->dev, "no device found, disabling link.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct ata_host *host = dev_get_drvdata(ap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct imx_ahci_priv *imxpriv = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (imxpriv->type == AHCI_IMX53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = ahci_ops.softreset(link, class, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static struct ata_port_operations ahci_imx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .host_stop = ahci_imx_host_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .error_handler = ahci_imx_error_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .softreset = ahci_imx_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const struct ata_port_info ahci_imx_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .port_ops = &ahci_imx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const struct of_device_id imx_ahci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) { .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct reg_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 of_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct reg_property {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) const struct reg_value *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) size_t num_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 def_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct reg_value gpr13_tx_level[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) { 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) { 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) { 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) { 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) { 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) { 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) { 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static const struct reg_value gpr13_tx_boost[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) { 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) { 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) { 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static const struct reg_value gpr13_tx_atten[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) { 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const struct reg_value gpr13_rx_eq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) { 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const struct reg_property gpr13_props[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .name = "fsl,transmit-level-mV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .values = gpr13_tx_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .num_values = ARRAY_SIZE(gpr13_tx_level),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .name = "fsl,transmit-boost-mdB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .values = gpr13_tx_boost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .num_values = ARRAY_SIZE(gpr13_tx_boost),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .name = "fsl,transmit-atten-16ths",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .values = gpr13_tx_atten,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .num_values = ARRAY_SIZE(gpr13_tx_atten),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .name = "fsl,receive-eq-mdB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .values = gpr13_rx_eq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .num_values = ARRAY_SIZE(gpr13_rx_eq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .name = "fsl,no-spread-spectrum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .set_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static u32 imx_ahci_parse_props(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) const struct reg_property *prop, size_t num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u32 reg_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) for (i = 0; i < num; i++, prop++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u32 of_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (prop->num_values == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (of_property_read_bool(np, prop->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) reg_value |= prop->set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) reg_value |= prop->def_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (of_property_read_u32(np, prop->name, &of_val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev_info(dev, "%s not specified, using %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) prop->name, prop->def_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) reg_value |= prop->def_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) for (j = 0; j < prop->num_values; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (prop->values[j].of_value == of_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dev_info(dev, "%s value %u, using %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) prop->name, of_val, prop->values[j].reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) reg_value |= prop->values[j].reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (j == prop->num_values) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dev_err(dev, "DT property %s is not a valid value\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) prop->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) reg_value |= prop->def_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static struct scsi_host_template ahci_platform_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) AHCI_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct resource *phy_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct platform_device *pdev = imxpriv->ahci_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (phy_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) imxpriv->phy_base = devm_ioremap(dev, phy_res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) resource_size(phy_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (!imxpriv->phy_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_err(dev, "error with ioremap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dev_err(dev, "missing *phy* reg region.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) imxpriv->gpr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) syscon_regmap_lookup_by_phandle(np, "hsio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (IS_ERR(imxpriv->gpr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev_err(dev, "unable to find gpr registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return PTR_ERR(imxpriv->gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (IS_ERR(imxpriv->epcs_tx_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_err(dev, "can't get epcs_tx_clk clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return PTR_ERR(imxpriv->epcs_tx_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (IS_ERR(imxpriv->epcs_rx_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dev_err(dev, "can't get epcs_rx_clk clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return PTR_ERR(imxpriv->epcs_rx_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (IS_ERR(imxpriv->phy_pclk0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dev_err(dev, "can't get phy_pclk0 clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return PTR_ERR(imxpriv->phy_pclk0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (IS_ERR(imxpriv->phy_pclk1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_err(dev, "can't get phy_pclk1 clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return PTR_ERR(imxpriv->phy_pclk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (IS_ERR(imxpriv->phy_apbclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) dev_err(dev, "can't get phy_apbclk clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return PTR_ERR(imxpriv->phy_apbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Fetch GPIO, then enable the external OSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) imxpriv->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (IS_ERR(imxpriv->clkreq_gpiod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return PTR_ERR(imxpriv->clkreq_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (imxpriv->clkreq_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int imx_ahci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct imx_ahci_priv *imxpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) unsigned int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) of_id = of_match_device(imx_ahci_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (!imxpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) imxpriv->ahci_pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) imxpriv->no_device = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) imxpriv->first_time = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) imxpriv->type = (enum ahci_imx_type)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) imxpriv->sata_clk = devm_clk_get(dev, "sata");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (IS_ERR(imxpriv->sata_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dev_err(dev, "can't get sata clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return PTR_ERR(imxpriv->sata_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (IS_ERR(imxpriv->sata_ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev_err(dev, "can't get sata_ref clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return PTR_ERR(imxpriv->sata_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (IS_ERR(imxpriv->ahb_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev_err(dev, "can't get ahb clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return PTR_ERR(imxpriv->ahb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) imxpriv->gpr = syscon_regmap_lookup_by_compatible(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "fsl,imx6q-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (IS_ERR(imxpriv->gpr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "failed to find fsl,imx6q-iomux-gpr regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return PTR_ERR(imxpriv->gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) reg_value = imx_ahci_parse_props(dev, gpr13_props,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ARRAY_SIZE(gpr13_props));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) imxpriv->phy_params =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) } else if (imxpriv->type == AHCI_IMX8QM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret = imx8_sata_probe(dev, imxpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) hpriv = ahci_platform_get_resources(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (IS_ERR(hpriv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return PTR_ERR(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) hpriv->plat_data = imxpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ret = clk_prepare_enable(imxpriv->sata_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (imxpriv->type == AHCI_IMX53 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) IS_ENABLED(CONFIG_HWMON)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* Add the temperature monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) hwmon_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) devm_hwmon_device_register_with_groups(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) "sata_ahci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) hpriv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) fsl_sata_ahci_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (IS_ERR(hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = PTR_ERR(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) devm_thermal_zone_of_sensor_register(hwmon_dev, 0, hwmon_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) &fsl_sata_ahci_of_thermal_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = imx_sata_enable(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * and IP vendor specific register IMX_TIMER1MS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * Configure CAP_SSS (support stagered spin up).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * Implement the port0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * Get the ahb clock rate, and configure the TIMER1MS register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) reg_val = readl(hpriv->mmio + HOST_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (!(reg_val & HOST_CAP_SSS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) reg_val |= HOST_CAP_SSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) writel(reg_val, hpriv->mmio + HOST_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (!(reg_val & 0x1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) reg_val |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) &ahci_platform_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) goto disable_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) disable_sata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) imx_sata_disable(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) clk_disable_unprepare(imxpriv->sata_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static void ahci_imx_host_stop(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct imx_ahci_priv *imxpriv = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) imx_sata_disable(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) clk_disable_unprepare(imxpriv->sata_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static int imx_ahci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = ahci_platform_suspend_host(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) imx_sata_disable(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static int imx_ahci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = imx_sata_enable(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return ahci_platform_resume_host(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static struct platform_driver imx_ahci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .probe = imx_ahci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .of_match_table = imx_ahci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .pm = &ahci_imx_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) module_platform_driver(imx_ahci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) MODULE_ALIAS("ahci:imx");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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