^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DaVinci DM816 AHCI SATA platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 BayLibre SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AHCI_DM816_DRV_NAME "ahci-dm816"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AHCI_DM816_PHY_ENPLL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AHCI_DM816_PHY_MPY(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AHCI_DM816_PHY_LOS(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AHCI_DM816_PHY_RXCDR(x) ((x) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AHCI_DM816_PHY_RXEQ(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AHCI_DM816_PHY_TXSWING(x) ((x) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AHCI_DM816_P0PHYCR_REG 0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AHCI_DM816_P1PHYCR_REG 0x1f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AHCI_DM816_PLL_OUT 1500000000LU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const unsigned long pll_mpy_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 400, 500, 600, 800, 825, 1000, 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 1250, 1500, 1600, 1650, 2000, 2200, 2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int ahci_dm816_get_mpy_bits(unsigned long refclk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long pll_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * We need to determine the value of the multiplier (MPY) bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * In order to include the 8.25 multiplier we need to first divide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * the refclk rate by 100.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pll_multiplier = AHCI_DM816_PLL_OUT / (refclk_rate / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) for (i = 0; i < ARRAY_SIZE(pll_mpy_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (pll_mpy_table[i] == pll_multiplier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * We should have divided evenly - if not, return an invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int ahci_dm816_phy_init(struct ahci_host_priv *hpriv, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long refclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int mpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * We should have been supplied two clocks: the functional and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * keep-alive clock and the external reference clock. We need the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * rate of the latter to calculate the correct value of MPY bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!hpriv->clks[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dev_err(dev, "reference clock not supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) refclk_rate = clk_get_rate(hpriv->clks[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if ((refclk_rate % 100) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev_err(dev, "reference clock rate must be divisible by 100\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mpy = ahci_dm816_get_mpy_bits(refclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (mpy < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_err(dev, "can't calculate the MPY bits value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Enable the PHY and configure the first HBA port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val = AHCI_DM816_PHY_MPY(mpy) | AHCI_DM816_PHY_LOS(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) AHCI_DM816_PHY_RXCDR(4) | AHCI_DM816_PHY_RXEQ(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) AHCI_DM816_PHY_TXSWING(3) | AHCI_DM816_PHY_ENPLL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(val, hpriv->mmio + AHCI_DM816_P0PHYCR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Configure the second HBA port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val = AHCI_DM816_PHY_LOS(1) | AHCI_DM816_PHY_RXCDR(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) AHCI_DM816_PHY_RXEQ(1) | AHCI_DM816_PHY_TXSWING(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(val, hpriv->mmio + AHCI_DM816_P1PHYCR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int ahci_dm816_softreset(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int *class, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int pmp, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pmp = sata_srst_pmp(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * There's an issue with the SATA controller on DM816 SoC: if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * enable Port Multiplier support, but the drive is connected directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * to the board, it can't be detected. As a workaround: if PMP is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * enabled, we first call ahci_do_softreset() and pass it the result of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * sata_srst_pmp(). If this call fails, we retry with pmp = 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (pmp && ret == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ahci_do_softreset(link, class, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) deadline, ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct ata_port_operations ahci_dm816_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .inherits = &ahci_platform_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .softreset = ahci_dm816_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct ata_port_info ahci_dm816_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .port_ops = &ahci_dm816_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct scsi_host_template ahci_dm816_platform_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) AHCI_SHT(AHCI_DM816_DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int ahci_dm816_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) hpriv = ahci_platform_get_resources(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (IS_ERR(hpriv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return PTR_ERR(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rc = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) rc = ahci_dm816_phy_init(hpriv, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rc = ahci_platform_init_host(pdev, hpriv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) &ahci_dm816_port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) &ahci_dm816_platform_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static SIMPLE_DEV_PM_OPS(ahci_dm816_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ahci_platform_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ahci_platform_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct of_device_id ahci_dm816_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .compatible = "ti,dm816-ahci", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MODULE_DEVICE_TABLE(of, ahci_dm816_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct platform_driver ahci_dm816_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .probe = ahci_dm816_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .name = AHCI_DM816_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .of_match_table = ahci_dm816_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .pm = &ahci_dm816_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) module_platform_driver(ahci_dm816_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MODULE_DESCRIPTION("DaVinci DM816 AHCI SATA platform driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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