Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DaVinci DA850 AHCI SATA platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DRV_NAME		"ahci_da850"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define HARDRESET_RETRIES	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* SATA PHY Control Register offset from AHCI base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SATA_P0PHYCR_REG	0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SATA_PHY_MPY(x)		((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SATA_PHY_LOS(x)		((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SATA_PHY_RXCDR(x)	((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SATA_PHY_RXEQ(x)	((x) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SATA_PHY_TXSWING(x)	((x) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SATA_PHY_ENPLL(x)	((x) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 			    void __iomem *ahci_base, u32 mpy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	/* Enable SATA clock receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	val = readl(pwrdn_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	val &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	writel(val, pwrdn_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	val = SATA_PHY_MPY(mpy) | SATA_PHY_LOS(1) | SATA_PHY_RXCDR(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	      SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | SATA_PHY_ENPLL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	writel(val, ahci_base + SATA_P0PHYCR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static u32 ahci_da850_calculate_mpy(unsigned long refclk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32 pll_output = 1500000000, needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 * We need to determine the value of the multiplier (MPY) bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	 * In order to include the 12.5 multiplier we need to first divide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 * the refclk rate by ten.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 * __div64_32() turned out to be unreliable, sometimes returning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 * false results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	needed = pll_output / (refclk_rate / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * What we have now is (multiplier * 10).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * Let's determine the actual register value we need to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	switch (needed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	case 60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	case 80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	case 100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return 0x5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	case 120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return 0x6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	case 125:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		return 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	case 150:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	case 200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		return 0x9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	case 250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return 0xa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		 * We should have divided evenly - if not, return an invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		 * value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int ahci_da850_softreset(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				unsigned int *class, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int pmp, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	pmp = sata_srst_pmp(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 * There's an issue with the SATA controller on da850 SoCs: if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * enable Port Multiplier support, but the drive is connected directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * to the board, it can't be detected. As a workaround: if PMP is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * enabled, we first call ahci_do_softreset() and pass it the result of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * sata_srst_pmp(). If this call fails, we retry with pmp = 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (pmp && ret == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return ahci_do_softreset(link, class, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 					 deadline, ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int ahci_da850_hardreset(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				unsigned int *class, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	int ret, retry = HARDRESET_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	bool online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * In order to correctly service the LCD controller of the da850 SoC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 * we increased the PLL0 frequency to 456MHz from the default 300MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 * This made the SATA controller unstable and the hardreset operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * does not always succeed the first time. Before really giving up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 * bring up the link, retry the reset a couple times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		ret = ahci_do_hardreset(link, class, deadline, &online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if (online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	} while (retry--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct ata_port_operations ahci_da850_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.inherits = &ahci_platform_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.softreset = ahci_da850_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 * No need to override .pmp_softreset - it's only used for actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 * PMP-enabled ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.hardreset = ahci_da850_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.pmp_hardreset = ahci_da850_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct ata_port_info ahci_da850_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.flags		= AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.udma_mask	= ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.port_ops	= &ahci_da850_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct scsi_host_template ahci_platform_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	AHCI_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int ahci_da850_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	void __iomem *pwrdn_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 mpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	hpriv = ahci_platform_get_resources(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (IS_ERR(hpriv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return PTR_ERR(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * Internally ahci_platform_get_resources() calls clk_get(dev, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 * when trying to obtain the functional clock. This SATA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 * uses two clocks for which we specify two connection ids. If we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 * have the functional clock at this point - call clk_get() again with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * con_id = "fck".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (!hpriv->clks[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		clk = clk_get(dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		hpriv->clks[0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 * The second clock used by ahci-da850 is the external REFCLK. If we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * didn't get it from ahci_platform_get_resources(), let's try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * specify the con_id in clk_get().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (!hpriv->clks[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		clk = clk_get(dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			dev_err(dev, "unable to obtain the reference clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		hpriv->clks[1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (mpy == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	rc = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (!pwrdn_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 				     &ahci_platform_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			 ahci_platform_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct of_device_id ahci_da850_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	{ .compatible = "ti,da850-ahci", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MODULE_DEVICE_TABLE(of, ahci_da850_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct platform_driver ahci_da850_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.probe = ahci_da850_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.of_match_table = ahci_da850_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.pm = &ahci_da850_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) module_platform_driver(ahci_da850_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_LICENSE("GPL");