Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2015 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * CEVA AHCI SATA platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* Vendor Specific Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AHCI_VEND_PCFG  0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AHCI_VEND_PPCFG 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AHCI_VEND_PP2C  0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AHCI_VEND_PP3C  0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AHCI_VEND_PP4C  0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AHCI_VEND_PP5C  0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AHCI_VEND_AXICC 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AHCI_VEND_PAXIC 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AHCI_VEND_PTC   0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Vendor Specific Register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PAXIC_ADBW_BW64 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PAXIC_MAWID(i)	(((i) * 2) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PAXIC_MARID(i)	(((i) * 2) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PAXIC_MARIDD(i)	((((i) * 2) + 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PAXIC_MAWIDD(i)	((((i) * 2) + 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PAXIC_OTL	(0x4 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Register bit definitions for cache control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AXICC_ARCA_VAL  (0xF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AXICC_ARCF_VAL  (0xF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AXICC_ARCH_VAL  (0xF << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AXICC_ARCP_VAL  (0xF << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AXICC_AWCFD_VAL (0xF << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AXICC_AWCD_VAL  (0xF << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AXICC_AWCF_VAL  (0xF << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PCFG_TPSS_VAL	(0x32 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCFG_TPRS_VAL	(0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PCFG_PAD_VAL	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PPCFG_TTA	0x1FFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PPCFG_PSSO_EN	(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PPCFG_PSS_EN	(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PPCFG_ESDF_EN	(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PP5C_RIT	0x60216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PP5C_RCT	(0x7f0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PTC_RX_WM_VAL	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PTC_RSVD	(1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PORT0_BASE	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PORT1_BASE	0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* Port Control Register Bit Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PORT_SCTL_SPD_GEN3	(0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PORT_SCTL_SPD_GEN2	(0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PORT_SCTL_SPD_GEN1	(0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PORT_SCTL_IPM		(0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PORT_BASE	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PORT_OFFSET	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define NR_PORTS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DRV_NAME	"ahci-ceva"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CEVA_FLAG_BROKEN_GEN2	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static unsigned int rx_watermark = PTC_RX_WM_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) module_param(rx_watermark, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) struct ceva_ahci_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct platform_device *ahci_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* Port Phy2Cfg Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 pp2c[NR_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 pp3c[NR_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32 pp4c[NR_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u32 pp5c[NR_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* Axi Cache Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32 axicc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	bool is_cci_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static unsigned int ceva_ahci_read_id(struct ata_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 					struct ata_taskfile *tf, u16 *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	err_mask = ata_do_dev_read_id(dev, tf, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (err_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 * Since CEVA controller does not support device sleep feature, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * need to clear DEVSLP (bit 8) in word78 of the IDENTIFY DEVICE data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct ata_port_operations ahci_ceva_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.inherits = &ahci_platform_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.read_id = ceva_ahci_read_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct ata_port_info ahci_ceva_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.flags          = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.pio_mask       = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.udma_mask      = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.port_ops	= &ahci_ceva_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct ceva_ahci_priv *cevapriv = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* Set AHCI Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	tmp = readl(mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	tmp |= HOST_AHCI_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	writel(tmp, mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	for (i = 0; i < NR_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		/* TPSS TPRS scalars, CISE and Port Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		writel(tmp, mmio + AHCI_VEND_PCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		 * AXI Data bus width to 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		 * Set Mem Addr Read, Write ID for data transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 * Set Mem Addr Read ID, Write ID for non-data transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 * Transfer limit to 72 DWord
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD(i) | PAXIC_MARIDD(i) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			PAXIC_MAWID(i) | PAXIC_MARID(i) | PAXIC_OTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		writel(tmp, mmio + AHCI_VEND_PAXIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		/* Set AXI cache control register if CCi is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (cevapriv->is_cci_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			tmp = readl(mmio + AHCI_VEND_AXICC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			tmp |= AXICC_ARCA_VAL | AXICC_ARCF_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				AXICC_ARCH_VAL | AXICC_ARCP_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				AXICC_AWCFD_VAL | AXICC_AWCD_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				AXICC_AWCF_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			writel(tmp, mmio + AHCI_VEND_AXICC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		/* Port Phy Cfg register enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		writel(tmp, mmio + AHCI_VEND_PPCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		/* Phy Control OOB timing parameters COMINIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		/* Phy Control OOB timing parameters COMWAKE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		/* Phy Control Burst timing setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		/* Rate Change Timer and Retry Interval Timer setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		/* Rx Watermark setting  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		tmp = rx_watermark | PTC_RSVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		writel(tmp, mmio + AHCI_VEND_PTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		/* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct scsi_host_template ahci_platform_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	AHCI_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int ceva_ahci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct ceva_ahci_priv *cevapriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	enum dev_dma_attr attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (!cevapriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	cevapriv->ahci_pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	hpriv = ahci_platform_get_resources(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (IS_ERR(hpriv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return PTR_ERR(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	rc = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (of_property_read_bool(np, "ceva,broken-gen2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* Read OOB timing value for COMINIT from device-tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (of_property_read_u8_array(np, "ceva,p0-cominit-params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 					(u8 *)&cevapriv->pp2c[0], 4) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		dev_warn(dev, "ceva,p0-cominit-params property not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (of_property_read_u8_array(np, "ceva,p1-cominit-params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 					(u8 *)&cevapriv->pp2c[1], 4) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_warn(dev, "ceva,p1-cominit-params property not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/* Read OOB timing value for COMWAKE from device-tree*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (of_property_read_u8_array(np, "ceva,p0-comwake-params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					(u8 *)&cevapriv->pp3c[0], 4) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		dev_warn(dev, "ceva,p0-comwake-params property not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (of_property_read_u8_array(np, "ceva,p1-comwake-params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 					(u8 *)&cevapriv->pp3c[1], 4) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		dev_warn(dev, "ceva,p1-comwake-params property not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* Read phy BURST timing value from device-tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (of_property_read_u8_array(np, "ceva,p0-burst-params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 					(u8 *)&cevapriv->pp4c[0], 4) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		dev_warn(dev, "ceva,p0-burst-params property not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (of_property_read_u8_array(np, "ceva,p1-burst-params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 					(u8 *)&cevapriv->pp4c[1], 4) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		dev_warn(dev, "ceva,p1-burst-params property not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* Read phy RETRY interval timing value from device-tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (of_property_read_u16_array(np, "ceva,p0-retry-params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 					(u16 *)&cevapriv->pp5c[0], 2) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		dev_warn(dev, "ceva,p0-retry-params property not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (of_property_read_u16_array(np, "ceva,p1-retry-params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 					(u16 *)&cevapriv->pp5c[1], 2) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		dev_warn(dev, "ceva,p1-retry-params property not defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	 * Check if CCI is enabled for SATA. The DEV_DMA_COHERENT is returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 * if CCI is enabled, so check for DEV_DMA_COHERENT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	attr = device_get_dma_attr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	cevapriv->is_cci_enabled = (attr == DEV_DMA_COHERENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	hpriv->plat_data = cevapriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* CEVA specific initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	ahci_ceva_setup(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	rc = ahci_platform_init_host(pdev, hpriv, &ahci_ceva_port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 					&ahci_platform_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int __maybe_unused ceva_ahci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return ahci_platform_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int __maybe_unused ceva_ahci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	rc = ahci_platform_enable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/* Configure CEVA specific config before resuming HBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ahci_ceva_setup(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	rc = ahci_platform_resume_host(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		goto disable_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/* We resumed so update PM runtime state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) disable_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	ahci_platform_disable_resources(hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct of_device_id ceva_ahci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{ .compatible = "ceva,ahci-1v84" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MODULE_DEVICE_TABLE(of, ceva_ahci_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct platform_driver ceva_ahci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.probe = ceva_ahci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.of_match_table = ceva_ahci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.pm = &ahci_ceva_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) module_platform_driver(ceva_ahci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_DESCRIPTION("CEVA AHCI SATA platform driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_AUTHOR("Xilinx Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MODULE_LICENSE("GPL v2");