^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ahci.h - Common AHCI SATA definitions and declarations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintained by: Tejun Heo <tj@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Please ALWAYS copy linux-ide@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * on emails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2004-2005 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * AHCI hardware documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef _AHCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define _AHCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Enclosure Management Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EM_CTRL_MSG_TYPE 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Enclosure Management LED Message Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EM_MSG_LED_HBA_PORT 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EM_MSG_LED_PMP_SLOT 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EM_MSG_LED_VALUE 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EM_MSG_LED_VALUE_OFF 0xfff80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EM_MSG_LED_VALUE_ON 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) AHCI_MAX_PORTS = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) AHCI_MAX_CLKS = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) AHCI_MAX_SG = 168, /* hardware max is 64K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) AHCI_DMA_BOUNDARY = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) AHCI_MAX_CMDS = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) AHCI_CMD_SZ = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) AHCI_RX_FIS_SZ = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) AHCI_CMD_TBL_CDB = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) AHCI_CMD_TBL_HDR_SZ = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) AHCI_RX_FIS_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) AHCI_CMD_TBL_AR_SZ +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (AHCI_RX_FIS_SZ * 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) AHCI_IRQ_ON_SG = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) AHCI_CMD_ATAPI = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) AHCI_CMD_WRITE = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) AHCI_CMD_PREFETCH = (1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) AHCI_CMD_RESET = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) AHCI_CMD_CLR_BUSY = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* global controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) HOST_CAP = 0x00, /* host capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) HOST_CTL = 0x04, /* global host control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) HOST_IRQ_STAT = 0x08, /* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) HOST_EM_LOC = 0x1c, /* Enclosure Management location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) HOST_EM_CTL = 0x20, /* Enclosure Management Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) HOST_CAP2 = 0x24, /* host capabilities, extended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* HOST_CTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) HOST_RESET = (1 << 0), /* reset controller; self-clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* HOST_CAP bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) HOST_CAP_PART = (1 << 13), /* Partial state capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) HOST_CAP_CLO = (1 << 24), /* Command List Override support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) HOST_CAP_LED = (1 << 25), /* Supports activity LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) HOST_CAP_SNTF = (1 << 29), /* SNotification register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* HOST_CAP2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) HOST_CAP2_SDS = (1 << 3), /* Support device sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* registers for each SATA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PORT_LST_ADDR = 0x00, /* command list DMA addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PORT_IRQ_STAT = 0x10, /* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PORT_CMD = 0x18, /* port command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PORT_TFDATA = 0x20, /* taskfile data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PORT_SIG = 0x24, /* device TF signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PORT_CMD_ISSUE = 0x38, /* command issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PORT_FBS = 0x40, /* FIS-based Switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PORT_DEVSLP = 0x44, /* device sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* PORT_IRQ_{STAT,MASK} bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PORT_IRQ_IF_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PORT_IRQ_CONNECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PORT_IRQ_PHYRDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PORT_IRQ_UNK_FIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PORT_IRQ_BAD_PMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PORT_IRQ_TF_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PORT_IRQ_HBUS_DATA_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* PORT_CMD bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PORT_CMD_ESP = (1 << 21), /* External Sata Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PORT_CMD_PMP = (1 << 17), /* PMP attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PORT_CMD_CLO = (1 << 3), /* Command list override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* PORT_FBS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PORT_FBS_SDE = (1 << 2), /* FBS single device error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PORT_FBS_EN = (1 << 0), /* Enable FBS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* PORT_DEVSLP bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* hpriv->flags bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) AHCI_HFLAG_NO_NCQ = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) link offline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) port start (wait until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) error-handling stage) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* compile out MSI infrastructure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) AHCI_HFLAG_MULTI_MSI = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) only registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) AHCI_HFLAG_IS_MOBILE = (1 << 25), /* mobile chipset, use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) SATA_MOBILE_LPM_POLICY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) as default lpm_policy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) AHCI_HFLAG_IGN_NOTSUPP_POWER_ON = (1 << 27), /* ignore -EOPNOTSUPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) from phy_power_on() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* ap->flags bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ICH_MAP = 0x90, /* ICH MAP register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PCS_6 = 0x92, /* 6 port PCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PCS_7 = 0x94, /* 7+ port PCS (Denverton) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* em constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) EM_MAX_SLOTS = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) EM_MAX_RETRY = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* em_ctl bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) EM_CTL_RST = (1 << 9), /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) EM_CTL_TM = (1 << 8), /* Transmit Message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) EM_CTL_MR = (1 << 0), /* Message Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) EM_CTL_ALHD = (1 << 26), /* Activity LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) EM_CTL_XMT = (1 << 25), /* Transmit Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) EM_CTL_SMB = (1 << 24), /* Single Message Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) EM_CTL_SES = (1 << 18), /* SES-2 messages supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) EM_CTL_LED = (1 << 16), /* LED messages supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* em message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) EM_MSG_TYPE_LED = (1 << 0), /* LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct ahci_cmd_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) __le32 opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __le32 tbl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) __le32 tbl_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __le32 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct ahci_sg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __le32 addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __le32 flags_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct ahci_em_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) enum sw_activity blink_policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned long saved_activity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long activity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned long led_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct ata_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct ahci_port_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct ata_link *active_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct ahci_cmd_hdr *cmd_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dma_addr_t cmd_slot_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) void *cmd_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dma_addr_t cmd_tbl_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) void *rx_fis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dma_addr_t rx_fis_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* for NCQ spurious interrupt analysis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int ncq_saw_d2h:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int ncq_saw_dmas:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned int ncq_saw_sdb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spinlock_t lock; /* protects parent ata_port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 intr_mask; /* interrupts to enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) bool fbs_supported; /* set iff FBS is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) bool fbs_enabled; /* set iff FBS is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int fbs_last_dev; /* save FBS.DEV of last FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* enclosure management info per PM slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct ahci_em_priv em_priv[EM_MAX_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) char *irq_desc; /* desc in /proc/interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct ahci_host_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Input fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned int flags; /* AHCI_HFLAG_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 force_port_map; /* force port map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 mask_port_map; /* mask out particular bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void __iomem * mmio; /* bus-independent mem map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 cap; /* cap to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 cap2; /* cap2 to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 version; /* cached version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 port_map; /* port map to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 saved_cap; /* saved initial cap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 saved_cap2; /* saved initial cap2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 saved_port_map; /* saved initial port_map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 em_loc; /* enclosure management location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 em_buf_sz; /* EM buffer size in byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 em_msg_type; /* EM message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 remapped_nvme; /* NVMe remapped device count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bool got_runtime_pm; /* Did we do pm_runtime_get? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct reset_control *rsts; /* Optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct regulator **target_pwrs; /* Optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct regulator *ahci_regulator;/* Optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct regulator *phy_regulator;/* Optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * If platform uses PHYs. There is a 1:1 relation between the port number and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * the PHY position in this array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct phy **phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned nports; /* Number of ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) void *plat_data; /* Other platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int irq; /* interrupt line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Optional ahci_start_engine override, if not set this gets set to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * default ahci_start_engine during ahci_save_initial_config, this can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * be overridden anytime before the host is activated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) void (*start_engine)(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * Optional ahci_stop_engine override, if not set this gets set to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * default ahci_stop_engine during ahci_save_initial_config, this can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * be overridden anytime before the host is activated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int (*stop_engine)(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) irqreturn_t (*irq_handler)(int irq, void *dev_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* only required for per-port MSI(-X) support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int (*get_irq_vector)(struct ata_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) extern int ahci_ignore_sss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) extern struct device_attribute *ahci_shost_attrs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) extern struct device_attribute *ahci_sdev_attrs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * This must be instantiated by the edge drivers. Read the comments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * for ATA_BASE_SHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define AHCI_SHT(drv_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ATA_NCQ_SHT(drv_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .can_queue = AHCI_MAX_CMDS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .sg_tablesize = AHCI_MAX_SG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .dma_boundary = AHCI_DMA_BOUNDARY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .shost_attrs = ahci_shost_attrs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .sdev_attrs = ahci_sdev_attrs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) extern struct ata_port_operations ahci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) extern struct ata_port_operations ahci_platform_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) extern struct ata_port_operations ahci_pmp_retry_srst_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned int ahci_dev_classify(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) void ahci_save_initial_config(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct ahci_host_priv *hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void ahci_init_controller(struct ata_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int ahci_reset_controller(struct ata_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int ahci_do_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int pmp, unsigned long deadline,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int (*check_ready)(struct ata_link *link));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned long deadline, bool *online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int ahci_stop_engine(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void ahci_start_fis_rx(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) void ahci_start_engine(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int ahci_check_ready(struct ata_link *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ahci_kick_engine(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int ahci_port_resume(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void ahci_set_em_messages(struct ahci_host_priv *hpriv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct ata_port_info *pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int ahci_reset_em(struct ata_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) void ahci_print_info(struct ata_host *host, const char *scc_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) void ahci_error_handler(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static inline void __iomem *__ahci_port_base(struct ata_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int port_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return mmio + 0x100 + (port_no * 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static inline void __iomem *ahci_port_base(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return __ahci_port_base(ap->host, ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static inline int ahci_nr_ports(u32 cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return (cap & 0x1f) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #endif /* _AHCI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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