^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ahci.c - AHCI SATA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintained by: Tejun Heo <tj@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Please ALWAYS copy linux-ide@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * on emails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2004-2005 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * AHCI hardware documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/ahci-remap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRV_NAME "ahci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRV_VERSION "3.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) AHCI_PCI_BAR_STA2X11 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) AHCI_PCI_BAR_CAVIUM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) AHCI_PCI_BAR_LOONGSON = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) AHCI_PCI_BAR_ENMOTUS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) AHCI_PCI_BAR_STANDARD = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum board_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* board IDs by feature in alphabetical order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) board_ahci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) board_ahci_ign_iferr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) board_ahci_mobile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) board_ahci_nomsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) board_ahci_noncq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) board_ahci_nosntf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) board_ahci_yes_fbs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* board IDs for specific chipsets in alphabetical order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) board_ahci_al,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) board_ahci_avn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) board_ahci_mcp65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) board_ahci_mcp77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) board_ahci_mcp89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) board_ahci_mv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) board_ahci_sb600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) board_ahci_sb700, /* for SB700 and SB800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) board_ahci_vt8251,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * board IDs for Intel chipsets that support more than 6 ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * *and* end up needing the PCS quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) board_ahci_pcs7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* aliases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) board_ahci_mcp_linux = board_ahci_mcp65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) board_ahci_mcp67 = board_ahci_mcp65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) board_ahci_mcp73 = board_ahci_mcp65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) board_ahci_mcp79 = board_ahci_mcp77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void ahci_remove_one(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void ahci_shutdown_one(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static bool is_mcp89_apple(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int ahci_pci_device_runtime_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int ahci_pci_device_runtime_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int ahci_pci_device_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int ahci_pci_device_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct scsi_host_template ahci_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) AHCI_SHT("ahci"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct ata_port_operations ahci_vt8251_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .hardreset = ahci_vt8251_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct ata_port_operations ahci_p5wdh_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .hardreset = ahci_p5wdh_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct ata_port_operations ahci_avn_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .hardreset = ahci_avn_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct ata_port_info ahci_port_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* by features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [board_ahci] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [board_ahci_ign_iferr] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [board_ahci_mobile] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [board_ahci_nomsi] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [board_ahci_noncq] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [board_ahci_nosntf] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [board_ahci_yes_fbs] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* by chipsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [board_ahci_al] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [board_ahci_avn] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .port_ops = &ahci_avn_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [board_ahci_mcp65] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) AHCI_HFLAG_YES_NCQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [board_ahci_mcp77] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [board_ahci_mcp89] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [board_ahci_mv] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [board_ahci_sb600] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) AHCI_HFLAG_32BIT_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .port_ops = &ahci_pmp_retry_srst_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) [board_ahci_sb700] = { /* for SB700 and SB800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .port_ops = &ahci_pmp_retry_srst_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [board_ahci_vt8251] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .port_ops = &ahci_vt8251_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [board_ahci_pcs7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .port_ops = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct pci_device_id ahci_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Intel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* JMicron 360/1/3/5/6, match class to avoid IDE function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* JMicron 362B and 362C have an AHCI function with IDE class code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* May need to update quirk_jmicron_async_suspend() for additions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* ATI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Amazon's Annapurna Labs support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .class = PCI_CLASS_STORAGE_SATA_AHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .class_mask = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) board_ahci_al },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* AMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* AMD is using RAID class only for ahci controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* VIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* NVIDIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* SiS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* ST Microelectronics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Marvell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .class = PCI_CLASS_STORAGE_SATA_AHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .class_mask = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .driver_data = board_ahci_yes_fbs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .driver_data = board_ahci_yes_fbs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .driver_data = board_ahci_yes_fbs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .driver_data = board_ahci_yes_fbs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .driver_data = board_ahci_yes_fbs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .driver_data = board_ahci_yes_fbs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Promise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Asmedia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Samsung SSDs found on some macbooks. NCQ times out if MSI is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Enmotus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Loongson */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Generic, PCI class code for AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const struct dev_pm_ops ahci_pci_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ahci_pci_device_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static struct pci_driver ahci_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .id_table = ahci_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .probe = ahci_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .remove = ahci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .shutdown = ahci_shutdown_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .pm = &ahci_pci_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #if IS_ENABLED(CONFIG_PATA_MARVELL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int marvell_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int marvell_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) module_param(marvell_enable, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int mobile_lpm_policy = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) module_param(mobile_lpm_policy, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static void ahci_pci_save_initial_config(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_info(&pdev->dev, "JMB361 has only one port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) hpriv->force_port_map = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * Temporary Marvell 6145 hack: PATA port presence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * is asserted through the standard AHCI port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * presence register, as bit 4 (counting from 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (pdev->device == 0x6121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) hpriv->mask_port_map = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) hpriv->mask_port_map = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ahci_save_initial_config(&pdev->dev, hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void ahci_pci_init_controller(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct pci_dev *pdev = to_pci_dev(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) void __iomem *port_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (pdev->device == 0x6121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mv = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mv = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) port_mmio = __ahci_port_base(host, mv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) writel(0, port_mmio + PORT_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* clear port IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) tmp = readl(port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) writel(tmp, port_mmio + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ahci_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) bool online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) deadline, &online, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* vt8251 doesn't clear BSY on signature FIS reception,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * request follow-up softreset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return online ? -EAGAIN : rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) bool online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* clear D2H reception area to properly wait for D2H FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ata_tf_init(link->device, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) tf.command = ATA_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ata_tf_to_fis(&tf, 0, 0, d2h_fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) deadline, &online, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* The pseudo configuration device on SIMG4726 attached to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * ASUS P5W-DH Deluxe doesn't send signature FIS after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * hardreset if no device is attached to the first downstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * port && the pseudo device locks up on SRST w/ PMP==0. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * work around this, wait for !BSY only briefly. If BSY isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * cleared, perform CLO and proceed to IDENTIFY (achieved by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * Wait for two seconds. Devices attached to downstream port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * which can't process the following IDENTIFY after this will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * have to be reset again. For most cases, this should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * suffice while making probing snappish enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (online) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ahci_kick_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * It has been observed with some SSDs that the timing of events in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * link synchronization phase can leave the port in a state that can not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * be recovered by a SATA-hard-reset alone. The failing signature is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * SStatus.DET stuck at 1 ("Device presence detected but Phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * communication not established"). It was found that unloading and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * reloading the driver when this problem occurs allows the drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * connection to be recovered (DET advanced to 0x3). The critical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * component of reloading the driver is that the port state machines are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * reset by bouncing "port enable" in the AHCI PCS configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * register. So, reproduce that effect by bouncing a port whenever we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * see DET==1 after a reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) unsigned long tmo = deadline - jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) bool online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int rc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u32 sstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int port = ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct ata_host *host = ap->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct pci_dev *pdev = to_pci_dev(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* clear D2H reception area to properly wait for D2H FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ata_tf_init(link->device, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) tf.command = ATA_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ata_tf_to_fis(&tf, 0, 0, d2h_fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) rc = sata_link_hardreset(link, timing, deadline, &online,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ahci_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) (sstatus & 0xf) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ata_link_info(link, "avn bounce port%d\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pci_read_config_word(pdev, 0x92, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) val &= ~(1 << port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) pci_write_config_word(pdev, 0x92, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ata_msleep(ap, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) val |= 1 << port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pci_write_config_word(pdev, 0x92, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) deadline += tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) *class = ahci_dev_classify(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static void ahci_pci_disable_interrupts(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* AHCI spec rev1.1 section 8.3.3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * Software must disable interrupts prior to requesting a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * transition of the HBA to D3 state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ctl = readl(mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ctl &= ~HOST_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) writel(ctl, mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) readl(mmio + HOST_CTL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static int ahci_pci_device_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ahci_pci_disable_interrupts(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int ahci_pci_device_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) rc = ahci_reset_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ahci_pci_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int ahci_pci_device_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "BIOS update required for suspend/resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ahci_pci_disable_interrupts(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return ata_host_suspend(host, PMSG_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int ahci_pci_device_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Apple BIOS helpfully mangles the registers on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (is_mcp89_apple(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ahci_mcp89_apple_enable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) rc = ahci_reset_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ahci_pci_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) const int dma_bits = using_dac ? 64 : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * If the device fixup already set the dma_mask to some non-standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * value, don't extend it here. This happens on STA2X11, for example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * XXX: manipulating the DMA mask from platform code is completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * bogus, platform code should use dev->bus_dma_limit instead..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_err(&pdev->dev, "DMA enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static void ahci_pci_print_info(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct pci_dev *pdev = to_pci_dev(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u16 cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) const char *scc_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pci_read_config_word(pdev, 0x0a, &cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (cc == PCI_CLASS_STORAGE_IDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) scc_s = "IDE";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) else if (cc == PCI_CLASS_STORAGE_SATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) scc_s = "SATA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) else if (cc == PCI_CLASS_STORAGE_RAID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) scc_s = "RAID";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) scc_s = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ahci_print_info(host, scc_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * support PMP and the 4726 either directly exports the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * attached to the first downstream port or acts as a hardware storage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * controller and emulate a single ATA device (can be RAID 0/1 or some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * other configuration).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * When there's no device attached to the first downstream port of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * 4726, "Config Disk" appears, which is a pseudo ATA device to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * configure the 4726. However, ATA emulation of the device is very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * lame. It doesn't send signature D2H Reg FIS after the initial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * The following function works around the problem by always using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * hardreset on the port and not depending on receiving signature FIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * afterward. If signature FIS isn't received soon, ATA class is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * assumed without follow-up softreset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static void ahci_p5wdh_workaround(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const struct dmi_system_id sysids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .ident = "P5W DH Deluxe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) DMI_MATCH(DMI_SYS_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) "ASUSTEK COMPUTER INC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct pci_dev *pdev = to_pci_dev(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dmi_check_system(sysids)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct ata_port *ap = host->ports[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ap->ops = &ahci_p5wdh_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * booting in BIOS compatibility mode. We restore the registers but not ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) pci_read_config_dword(pdev, 0xf8, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) val |= 1 << 0x1b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* the following changes the device ID, but appears not to affect function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* val = (val & ~0xf0000000) | 0x80000000; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) pci_write_config_dword(pdev, 0xf8, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) pci_read_config_dword(pdev, 0x54c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) val |= 1 << 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pci_write_config_dword(pdev, 0x54c, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) pci_read_config_dword(pdev, 0x4a4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) val &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) val |= 0x01060100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) pci_write_config_dword(pdev, 0x4a4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) pci_read_config_dword(pdev, 0x54c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) val &= ~(1 << 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pci_write_config_dword(pdev, 0x54c, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pci_read_config_dword(pdev, 0xf8, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) val &= ~(1 << 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) pci_write_config_dword(pdev, 0xf8, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static bool is_mcp89_apple(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) pdev->subsystem_device == 0xcb89;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* only some SB600 ahci controllers can do 64bit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const struct dmi_system_id sysids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * The oldest version known to be broken is 0901 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * working is 1501 which was released on 2007-10-26.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * Enable 64bit DMA on 1501 and anything newer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * Please read bko#9412 for more info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .ident = "ASUS M2A-VM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) DMI_MATCH(DMI_BOARD_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .driver_data = "20071026", /* yyyymmdd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * support 64bit DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * BIOS versions earlier than 1.5 had the Manufacturer DMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * This spelling mistake was fixed in BIOS version 1.5, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * 1.5 and later have the Manufacturer as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * "MICRO-STAR INTERNATIONAL CO.,LTD".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * BIOS versions earlier than 1.9 had a Board Product Name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * DMI field of "MS-7376". This was changed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * match on DMI_BOARD_NAME of "MS-7376".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .ident = "MSI K9A2 Platinum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) DMI_MATCH(DMI_BOARD_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) "MICRO-STAR INTER"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * All BIOS versions for the MSI K9AGM2 (MS-7327) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * 64bit DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * This board also had the typo mentioned above in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * Manufacturer DMI field (fixed in BIOS version 1.5), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .ident = "MSI K9AGM2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) DMI_MATCH(DMI_BOARD_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) "MICRO-STAR INTER"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * All BIOS versions for the Asus M3A support 64bit DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * (all release versions from 0301 to 1206 were tested)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .ident = "ASUS M3A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) DMI_MATCH(DMI_BOARD_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) DMI_MATCH(DMI_BOARD_NAME, "M3A"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) const struct dmi_system_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int year, month, date;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) char buf[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) match = dmi_first_match(sysids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) !match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!match->driver_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) goto enable_64bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (strcmp(buf, match->driver_data) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) goto enable_64bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) match->ident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) enable_64bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static const struct dmi_system_id broken_systems[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .ident = "HP Compaq nx6310",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* PCI slot number of the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .driver_data = (void *)0x1FUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .ident = "HP Compaq 6720s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* PCI slot number of the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .driver_data = (void *)0x1FUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (dmi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) unsigned long slot = (unsigned long)dmi->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* apply the quirk only to on-board controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return slot == PCI_SLOT(pdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static bool ahci_broken_suspend(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static const struct dmi_system_id sysids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * On HP dv[4-6] and HDX18 with earlier BIOSen, link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * to the harddisk doesn't become online after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * resuming from STR. Warn and fail suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * http://bugzilla.kernel.org/show_bug.cgi?id=12276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * Use dates instead of versions to match as HP is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * apparently recycling both product and version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * strings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * http://bugzilla.kernel.org/show_bug.cgi?id=15462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .ident = "dv4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) DMI_MATCH(DMI_PRODUCT_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) "HP Pavilion dv4 Notebook PC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .driver_data = "20090105", /* F.30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .ident = "dv5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) DMI_MATCH(DMI_PRODUCT_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) "HP Pavilion dv5 Notebook PC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .driver_data = "20090506", /* F.16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .ident = "dv6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) DMI_MATCH(DMI_PRODUCT_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) "HP Pavilion dv6 Notebook PC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .driver_data = "20090423", /* F.21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .ident = "HDX18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) DMI_MATCH(DMI_PRODUCT_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) "HP HDX18 Notebook PC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .driver_data = "20090430", /* F.23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * Acer eMachines G725 has the same problem. BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * V1.03 is known to be broken. V3.04 is known to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * work. Between, there are V1.06, V2.06 and V3.03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * that we don't have much idea about. For now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * blacklist anything older than V3.04.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * http://bugzilla.kernel.org/show_bug.cgi?id=15104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .ident = "G725",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .driver_data = "20091216", /* V3.04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) const struct dmi_system_id *dmi = dmi_first_match(sysids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) int year, month, date;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) char buf[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return strcmp(buf, dmi->driver_data) < 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static bool ahci_broken_lpm(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static const struct dmi_system_id sysids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* Various Lenovo 50 series have LPM issues with older BIOSen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .driver_data = "20180406", /* 1.31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .driver_data = "20180420", /* 1.28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .driver_data = "20180315", /* 1.33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * Note date based on release notes, 2.35 has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * reported to be good, but I've been unable to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * a hold of the reporter to get the DMI BIOS date.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * TODO: fix this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .driver_data = "20180310", /* 2.35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) const struct dmi_system_id *dmi = dmi_first_match(sysids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) int year, month, date;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) char buf[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (!dmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return strcmp(buf, dmi->driver_data) < 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static bool ahci_broken_online(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define ENCODE_BUSDEVFN(bus, slot, func) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static const struct dmi_system_id sysids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * There are several gigabyte boards which use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * SIMG5723s configured as hardware RAID. Certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * 5723 firmware revisions shipped there keep the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * online but fail to answer properly to SRST or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * IDENTIFY when no device is attached downstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * causing libata to retry quite a few times leading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * to excessive detection delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * As these firmwares respond to the second reset try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * with invalid device signature, considering unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * sig as offline works around the problem acceptably.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .ident = "EP45-DQ6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) DMI_MATCH(DMI_BOARD_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) "Gigabyte Technology Co., Ltd."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .ident = "EP45-DS5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) DMI_MATCH(DMI_BOARD_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) "Gigabyte Technology Co., Ltd."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #undef ENCODE_BUSDEVFN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) const struct dmi_system_id *dmi = dmi_first_match(sysids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (!dmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) val = (unsigned long)dmi->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static bool ahci_broken_devslp(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* device with broken DEVSLP but still showing SDS capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static const struct pci_device_id ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return pci_match_id(ids, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #ifdef CONFIG_ATA_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static void ahci_gtf_filter_workaround(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static const struct dmi_system_id sysids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * Aspire 3810T issues a bunch of SATA enable commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * via _GTF including an invalid one and one which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * rejected by the device. Among the successful ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * is FPDMA non-zero offset enable which when enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * only on the drive side leads to NCQ command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * failures. Filter it out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .ident = "Aspire 3810T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) const struct dmi_system_id *dmi = dmi_first_match(sysids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) unsigned int filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (!dmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) filter = (unsigned long)dmi->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) filter, dmi->ident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct ata_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ata_for_each_link(link, ap, EDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ata_for_each_dev(dev, link, ALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) dev->gtf_filter |= filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static inline void ahci_gtf_filter_workaround(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * as DUMMY, or detected but eventually get a "link down" and never get up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * port_map may hold a value of 0x00.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * and can significantly reduce the occurrence of the problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * https://bugzilla.kernel.org/show_bug.cgi?id=189471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static const struct dmi_system_id sysids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .ident = "Acer Switch Alpha 12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (dmi_check_system(sysids)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) hpriv->port_map = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) hpriv->cap = 0xC734FF02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * Workaround is to make sure all pending IRQs are served before leaving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) unsigned int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) u32 irq_stat, irq_masked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) unsigned int handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) irq_stat = readl(mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (!irq_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) irq_masked = irq_stat & hpriv->port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) rc = ahci_handle_port_intr(host, irq_masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) writel(irq_stat, mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) irq_stat = readl(mmio + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) } while (irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) VPRINTK("EXIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static void ahci_remap_check(struct pci_dev *pdev, int bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) u32 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * Check if this device might have remapped nvme devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) pci_resource_len(pdev, bar) < SZ_512K ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) bar != AHCI_PCI_BAR_STANDARD ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) for (i = 0; i < AHCI_MAX_REMAP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if ((cap & (1 << i)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (readl(hpriv->mmio + ahci_remap_dcc(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) != PCI_CLASS_STORAGE_EXPRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* We've found a remapped device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) hpriv->remapped_nvme++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (!hpriv->remapped_nvme)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) hpriv->remapped_nvme);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) "Switch your BIOS from RAID to AHCI mode to use them.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * Don't rely on the msi-x capability in the remap case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * share the legacy interrupt across ahci and remapped devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) hpriv->flags |= AHCI_HFLAG_NO_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static int ahci_get_irq_vector(struct ata_host *host, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) return pci_irq_vector(to_pci_dev(host->dev), port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) int nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (hpriv->flags & AHCI_HFLAG_NO_MSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * If number of MSIs is less than number of ports then Sharing Last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) * Message mode could be enforced. In this case assume that advantage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * of multipe MSIs is negated and use single MSI mode instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (n_ports > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) PCI_IRQ_MSIX | PCI_IRQ_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (nvec > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) hpriv->get_irq_vector = ahci_get_irq_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) return nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * Fallback to single MSI mode if the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) * enforced MRSM mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) "ahci: MRSM is on, fallback to single MSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * If the host is not capable of supporting per-port vectors, fall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * back to single MSI before finally attempting single MSI-X.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (nvec == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static void ahci_update_initial_lpm_policy(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* Ignore processing for non mobile platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* user modified policy via module param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (mobile_lpm_policy != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) policy = mobile_lpm_policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) goto update_policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (policy > ATA_LPM_MED_POWER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (hpriv->cap & HOST_CAP_PART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) else if (hpriv->cap & HOST_CAP_SSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) policy = ATA_LPM_MIN_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) update_policy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) ap->target_lpm_policy = policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) u16 tmp16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * Only apply the 6-port PCS quirk for known legacy platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /* Skip applying the quirk on Denverton and beyond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * port_map is determined from PORTS_IMPL PCI register which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) * implemented as write or write-once register. If the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * isn't programmed, ahci automatically generates it from number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) * of ports, which is good enough for PCS programming. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) * otherwise expected that platform firmware enables the ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * before the OS boots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) pci_read_config_word(pdev, PCS_6, &tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) tmp16 |= hpriv->port_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) pci_write_config_word(pdev, PCS_6, tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static ssize_t remapped_nvme_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return sprintf(buf, "%u\n", hpriv->remapped_nvme);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static DEVICE_ATTR_RO(remapped_nvme);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) unsigned int board_id = ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) struct ata_port_info pi = ahci_port_info[board_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) const struct ata_port_info *ppi[] = { &pi, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) int n_ports, i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* The AHCI driver can only drive the SATA ports, the PATA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) can drive them all so if both drivers are selected make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) AHCI stays out of the way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /* Apple BIOS on MCP89 prevents us using AHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) if (is_mcp89_apple(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) ahci_mcp89_apple_enable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) * At the moment, we can only use the AHCI mode. Let the users know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) * that for SAS drives they're out of luck.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) "PDC42819 can only drive SATA devices with this driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) /* Some devices use non-standard BARs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (pdev->device == 0xa01c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (pdev->device == 0xa084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (pdev->device == 0x7a08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /* acquire resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) (pdev->device == 0x2652 || pdev->device == 0x2653)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) u8 map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /* ICH6s share the same PCI ID for both piix and ahci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) * modes. Enabling ahci mode while MAP indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) * combined mode is a bad idea. Yield to ata_piix.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) pci_read_config_byte(pdev, ICH_MAP, &map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (map & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) "controller is in combined mode, can't enable AHCI mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* AHCI controllers often implement SFF compatible interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * Grab all PCI BARs just in case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (rc == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) pcim_pin_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (!hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) hpriv->flags |= (unsigned long)pi.private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* MCP65 revision A1 and A2 can't do MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (board_id == board_ahci_mcp65 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) (pdev->revision == 0xa1 || pdev->revision == 0xa2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) hpriv->flags |= AHCI_HFLAG_NO_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) /* only some SB600s can do 64bit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (ahci_sb600_enable_64bit(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* detect remapped nvme devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) ahci_remap_check(pdev, ahci_pci_bar, hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) sysfs_add_file_to_group(&pdev->dev.kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) &dev_attr_remapped_nvme.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* must set flag prior to save config in order to take effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (ahci_broken_devslp(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) pdev->device == 0xa235 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) pdev->revision < 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) hpriv->flags |= AHCI_HFLAG_NO_SXS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) hpriv->irq_handler = ahci_thunderx_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) /* save initial config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) ahci_pci_save_initial_config(pdev, hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * If platform firmware failed to enable ports, try to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) * them here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) ahci_intel_pcs_quirk(pdev, hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) /* prepare host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) if (hpriv->cap & HOST_CAP_NCQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) pi.flags |= ATA_FLAG_NCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * Auto-activate optimization is supposed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * supported on all AHCI controllers indicating NCQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) * capability, but it seems to be broken on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) * chipsets including NVIDIAs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) pi.flags |= ATA_FLAG_FPDMA_AA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) * All AHCI controllers should be forward-compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) * with the new auxiliary field. This code should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) * conditionalized if any buggy AHCI controllers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * encountered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) pi.flags |= ATA_FLAG_FPDMA_AUX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (hpriv->cap & HOST_CAP_PMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) pi.flags |= ATA_FLAG_PMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) ahci_set_em_messages(hpriv, &pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) if (ahci_broken_system_poweroff(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) "quirky BIOS, skipping spindown on poweroff\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) if (ahci_broken_lpm(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) pi.flags |= ATA_FLAG_NO_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) "BIOS update required for Link Power Management support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (ahci_broken_suspend(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) "BIOS update required for suspend/resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (ahci_broken_online(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) "online status unreliable, applying workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /* Acer SA5-271 workaround modifies private_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) acer_sa5_271_workaround(hpriv, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /* CAP.NP sometimes indicate the index of the last enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) * port, at other times, that of the last possible port, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) * determining the maximum port number requires looking at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) * both CAP.NP and port_map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) host->private_data = hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /* legacy intx interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) pci_intx(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) hpriv->irq = pci_irq_vector(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) host->flags |= ATA_HOST_PARALLEL_SCAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (pi.flags & ATA_FLAG_EM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ahci_reset_em(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ata_port_pbar_desc(ap, ahci_pci_bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) 0x100 + ap->port_no * 0x80, "port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /* set enclosure management message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (ap->flags & ATA_FLAG_EM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) ap->em_message_type = hpriv->em_msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ahci_update_initial_lpm_policy(ap, hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* disabled/not-implemented port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (!(hpriv->port_map & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ap->ops = &ata_dummy_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) /* apply workaround for ASUS P5W DH Deluxe mainboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) ahci_p5wdh_workaround(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /* apply gtf filter quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) ahci_gtf_filter_workaround(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) /* initialize adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) rc = ahci_reset_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) ahci_pci_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) ahci_pci_print_info(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) rc = ahci_host_activate(host, &ahci_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static void ahci_shutdown_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ata_pci_shutdown_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static void ahci_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) sysfs_remove_file_from_group(&pdev->dev.kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) &dev_attr_remapped_nvme.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ata_pci_remove_one(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) module_pci_driver(ahci_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) MODULE_AUTHOR("Jeff Garzik");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) MODULE_DESCRIPTION("AHCI SATA low-level driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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