^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * acard-ahci.c - ACard AHCI SATA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maintained by: Tejun Heo <tj@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Please ALWAYS copy linux-ide@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * on emails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 2010 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * AHCI hardware documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRV_NAME "acard-ahci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRV_VERSION "1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Received FIS structure limited to 80h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ACARD_AHCI_RX_FIS_SZ 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) AHCI_PCI_BAR = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum board_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) board_acard_ahci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct acard_sg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __le32 addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __le32 size; /* bit 31 (EOT) max==0x10000 (64k) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int acard_ahci_port_start(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int acard_ahci_pci_device_resume(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct scsi_host_template acard_ahci_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) AHCI_SHT("acard-ahci"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct ata_port_operations acard_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .qc_prep = acard_ahci_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .qc_fill_rtf = acard_ahci_qc_fill_rtf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .port_start = acard_ahci_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct ata_port_info acard_ahci_port_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [board_acard_ahci] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .port_ops = &acard_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct pci_device_id acard_ahci_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* ACard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { PCI_VDEVICE(ARTOP, 0x000d), board_acard_ahci }, /* ATP8620 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct pci_driver acard_ahci_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .id_table = acard_ahci_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .probe = acard_ahci_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .suspend = acard_ahci_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .resume = acard_ahci_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (mesg.event & PM_EVENT_SUSPEND &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "BIOS update required for suspend/resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (mesg.event & PM_EVENT_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* AHCI spec rev1.1 section 8.3.3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Software must disable interrupts prior to requesting a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * transition of the HBA to D3 state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ctl = readl(mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ctl &= ~HOST_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(ctl, mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) readl(mmio + HOST_CTL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ata_pci_device_suspend(pdev, mesg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int acard_ahci_pci_device_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) rc = ahci_reset_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ahci_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void acard_ahci_pci_print_info(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct pci_dev *pdev = to_pci_dev(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u16 cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) const char *scc_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pci_read_config_word(pdev, 0x0a, &cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (cc == PCI_CLASS_STORAGE_IDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) scc_s = "IDE";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else if (cc == PCI_CLASS_STORAGE_SATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) scc_s = "SATA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) else if (cc == PCI_CLASS_STORAGE_RAID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) scc_s = "RAID";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) scc_s = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ahci_print_info(host, scc_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int si, last_si = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Next, the S/G list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) for_each_sg(qc->sg, sg, qc->n_elem, si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dma_addr_t addr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 sg_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * ACard note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * We must set an end-of-table (EOT) bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * and the segment cannot exceed 64k (0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) acard_sg[si].size = cpu_to_le32(sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) last_si = si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int is_atapi = ata_is_atapi(qc->tf.protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void *cmd_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const u32 cmd_fis_len = 5; /* five dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Fill in command table information. First, the header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * a SATA Register - Host to Device command FIS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (is_atapi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (qc->flags & ATA_QCFLAG_DMAMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) acard_ahci_fill_sg(qc, cmd_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Fill in command slot information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * ACard note: prd table length not filled in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) opts = cmd_fis_len | (qc->dev->link->pmp << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (qc->tf.flags & ATA_TFLAG_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) opts |= AHCI_CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (is_atapi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct ahci_port_priv *pp = qc->ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 *rx_fis = pp->rx_fis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (pp->fbs_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * After a successful execution of an ATA PIO data-in command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * the device doesn't send D2H Reg FIS to update the TF and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * the host should take TF and E_Status from the preceding PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Setup FIS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) !(qc->flags & ATA_QCFLAG_FAILED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int acard_ahci_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct device *dev = ap->host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct ahci_port_priv *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dma_addr_t mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) size_t dma_sz, rx_fis_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (!pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* check FBS capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void __iomem *port_mmio = ahci_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 cmd = readl(port_mmio + PORT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (cmd & PORT_CMD_FBSCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pp->fbs_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pp->fbs_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_warn(dev, "port %d is not capable of FBS\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (pp->fbs_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dma_sz = AHCI_PORT_PRIV_DMA_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) rx_fis_sz = ACARD_AHCI_RX_FIS_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * First item in chunk of DMA memory: 32-slot command table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * 32 bytes each in size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pp->cmd_slot = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pp->cmd_slot_dma = mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mem += AHCI_CMD_SLOT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mem_dma += AHCI_CMD_SLOT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Second item: Received-FIS area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pp->rx_fis = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pp->rx_fis_dma = mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mem += rx_fis_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mem_dma += rx_fis_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Third item: data area for storing a single command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * and its scatter-gather table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pp->cmd_tbl = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pp->cmd_tbl_dma = mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Save off initial list of interrupts to be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * This could be changed later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pp->intr_mask = DEF_PORT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ap->private_data = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* engage engines, captain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ahci_port_resume(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int board_id = ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct ata_port_info pi = acard_ahci_port_info[board_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) const struct ata_port_info *ppi[] = { &pi, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int n_ports, i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* acquire resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* AHCI controllers often implement SFF compatible interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Grab all PCI BARs just in case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (rc == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pcim_pin_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hpriv->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) hpriv->flags |= (unsigned long)pi.private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pci_enable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* save initial config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ahci_save_initial_config(&pdev->dev, hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* prepare host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (hpriv->cap & HOST_CAP_NCQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pi.flags |= ATA_FLAG_NCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (hpriv->cap & HOST_CAP_PMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pi.flags |= ATA_FLAG_PMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ahci_set_em_messages(hpriv, &pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* CAP.NP sometimes indicate the index of the last enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * port, at other times, that of the last possible port, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * determining the maximum port number requires looking at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * both CAP.NP and port_map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) host->private_data = hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) host->flags |= ATA_HOST_PARALLEL_SCAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ata_port_pbar_desc(ap, AHCI_PCI_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x100 + ap->port_no * 0x80, "port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* set initial link pm policy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ap->pm_policy = NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* disabled/not-implemented port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!(hpriv->port_map & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ap->ops = &ata_dummy_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* initialize adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) rc = dma_set_mask_and_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 : 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(&pdev->dev, "DMA enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rc = ahci_reset_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ahci_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) acard_ahci_pci_print_info(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ahci_host_activate(host, &acard_ahci_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) module_pci_driver(acard_ahci_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MODULE_AUTHOR("Jeff Garzik");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MODULE_DESCRIPTION("ACard AHCI SATA low-level driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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