^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jay Cheng <jacheng@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * James Wylder <james.wylder@motorola.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Benoit Goby <benoit@android.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Colin Cross <ccross@android.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Hiroshi DOYU <hdoyu@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <soc/tegra/ahb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DRV_NAME "tegra-ahb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AHB_ARBITRATION_DISABLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AHB_ARBITRATION_PRIORITY_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PRIORITY_SELECT_USB BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PRIORITY_SELECT_USB2 BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PRIORITY_SELECT_USB3 BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AHB_GIZMO_AHB_MEM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ENB_FAST_REARBITRATE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DONT_SPLIT_AHB_WR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AHB_GIZMO_APB_DMA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AHB_GIZMO_IDE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AHB_GIZMO_USB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AHB_GIZMO_AHB_XBAR_BRIDGE 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AHB_GIZMO_CPU_AHB_BRIDGE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AHB_GIZMO_COP_AHB_BRIDGE 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AHB_GIZMO_XBAR_APB_CTLR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AHB_GIZMO_VCP_AHB_BRIDGE 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AHB_GIZMO_NAND 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AHB_GIZMO_SDMMC4 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AHB_GIZMO_XIO 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AHB_GIZMO_BSEV 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AHB_GIZMO_BSEA 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AHB_GIZMO_NOR 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AHB_GIZMO_USB2 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AHB_GIZMO_USB3 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMMEDIATE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AHB_GIZMO_SDMMC1 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AHB_GIZMO_SDMMC2 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AHB_GIZMO_SDMMC3 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AHB_MEM_PREFETCH_CFG_X 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AHB_ARBITRATION_XBAR_CTRL 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AHB_MEM_PREFETCH_CFG3 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AHB_MEM_PREFETCH_CFG4 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AHB_MEM_PREFETCH_CFG1 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AHB_MEM_PREFETCH_CFG2 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PREFETCH_ENB BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MST_ID(x) (((x) & 0x1f) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AHBDMA_MST_ID MST_ID(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define USB_MST_ID MST_ID(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define USB2_MST_ID MST_ID(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define USB3_MST_ID MST_ID(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADDR_BNDRY(x) (((x) & 0xf) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * INCORRECT_BASE_ADDR_LOW_BYTE: Legacy kernel DT files for Tegra SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * prior to Tegra124 generally use a physical base address ending in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * 0x4 for the AHB IP block. According to the TRM, the low byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * should be 0x0. During device probing, this macro is used to detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * whether the passed-in physical address is incorrect, and if so, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * correct it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define INCORRECT_BASE_ADDR_LOW_BYTE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct platform_driver tegra_ahb_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const u32 tegra_ahb_gizmo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) AHB_ARBITRATION_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) AHB_ARBITRATION_PRIORITY_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) AHB_GIZMO_AHB_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) AHB_GIZMO_APB_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) AHB_GIZMO_IDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) AHB_GIZMO_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) AHB_GIZMO_AHB_XBAR_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) AHB_GIZMO_CPU_AHB_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) AHB_GIZMO_COP_AHB_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) AHB_GIZMO_XBAR_APB_CTLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) AHB_GIZMO_VCP_AHB_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) AHB_GIZMO_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) AHB_GIZMO_SDMMC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) AHB_GIZMO_XIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) AHB_GIZMO_BSEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) AHB_GIZMO_BSEA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) AHB_GIZMO_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) AHB_GIZMO_USB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) AHB_GIZMO_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) AHB_GIZMO_SDMMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) AHB_GIZMO_SDMMC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) AHB_GIZMO_SDMMC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) AHB_MEM_PREFETCH_CFG_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) AHB_ARBITRATION_XBAR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) AHB_MEM_PREFETCH_CFG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) AHB_MEM_PREFETCH_CFG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) AHB_MEM_PREFETCH_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) AHB_MEM_PREFETCH_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct tegra_ahb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 ctx[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return readl(ahb->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(value, ahb->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef CONFIG_TEGRA_IOMMU_SMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int tegra_ahb_enable_smmu(struct device_node *dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct tegra_ahb *ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev = driver_find_device_by_of_node(&tegra_ahb_driver.driver, dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ahb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) EXPORT_SYMBOL(tegra_ahb_enable_smmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int __maybe_unused tegra_ahb_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct tegra_ahb *ahb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int __maybe_unused tegra_ahb_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct tegra_ahb *ahb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tegra_ahb_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) tegra_ahb_resume, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val = gizmo_readl(ahb, AHB_GIZMO_USB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val |= IMMEDIATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) gizmo_writel(ahb, val, AHB_GIZMO_USB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = gizmo_readl(ahb, AHB_GIZMO_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val |= IMMEDIATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) gizmo_writel(ahb, val, AHB_GIZMO_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val = gizmo_readl(ahb, AHB_GIZMO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val |= IMMEDIATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) gizmo_writel(ahb, val, AHB_GIZMO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) val |= PRIORITY_SELECT_USB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PRIORITY_SELECT_USB2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PRIORITY_SELECT_USB3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) AHB_PRIORITY_WEIGHT(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) val &= ~MST_ID(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val |= PREFETCH_ENB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) AHBDMA_MST_ID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ADDR_BNDRY(0xc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) INACTIVITY_TIMEOUT(0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val &= ~MST_ID(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val |= PREFETCH_ENB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) USB_MST_ID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ADDR_BNDRY(0xc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) INACTIVITY_TIMEOUT(0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) val &= ~MST_ID(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val |= PREFETCH_ENB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) USB3_MST_ID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ADDR_BNDRY(0xc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) INACTIVITY_TIMEOUT(0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val &= ~MST_ID(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val |= PREFETCH_ENB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) USB2_MST_ID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ADDR_BNDRY(0xc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) INACTIVITY_TIMEOUT(0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int tegra_ahb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct tegra_ahb *ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) size_t bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!ahb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Correct the IP block base address if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (res &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (res->start & INCORRECT_BASE_ADDR_LOW_BYTE) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) INCORRECT_BASE_ADDR_LOW_BYTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) res->start -= INCORRECT_BASE_ADDR_LOW_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ahb->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (IS_ERR(ahb->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return PTR_ERR(ahb->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ahb->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) platform_set_drvdata(pdev, ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) tegra_ahb_gizmo_init(ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct of_device_id tegra_ahb_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .compatible = "nvidia,tegra30-ahb", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .compatible = "nvidia,tegra20-ahb", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct platform_driver tegra_ahb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .probe = tegra_ahb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .of_match_table = tegra_ahb_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .pm = &tegra_ahb_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) module_platform_driver(tegra_ahb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MODULE_DESCRIPTION("Tegra AHB driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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