^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2015, Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015, 2016 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) "ACPI: SPCR: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * occasionally getting stuck as 1. To avoid the potential for a hang, check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * implementations, so only do so if an affected platform is detected in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * acpi_parse_spcr().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) bool qdf2400_e44_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) EXPORT_SYMBOL(qdf2400_e44_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Detect them by examining the OEM fields in the SPCR header, similar to PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * quirk detection in pci_mcfg.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static bool qdf2400_erratum_44_present(struct acpi_table_header *h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) h->oem_revision == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * APM X-Gene v1 and v2 UART hardware is an 16550 like device but has its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * register aligned to 32-bit. In addition, the BIOS also encoded the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * access width to be 8 bits. This function detects this errata condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bool xgene_8250 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (tb->interface_type != ACPI_DBG2_16550_COMPATIBLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) memcmp(tb->header.oem_id, "HPE ", ACPI_OEM_ID_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!memcmp(tb->header.oem_table_id, "XGENESPC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) xgene_8250 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!memcmp(tb->header.oem_table_id, "ProLiant",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) xgene_8250 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return xgene_8250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * acpi_parse_spcr() - parse ACPI SPCR table and add preferred console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @enable_earlycon: set up earlycon for the console specified by the table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @enable_console: setup the console specified by the table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * For the architectures with support for ACPI, CONFIG_ACPI_SPCR_TABLE may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * defined to parse ACPI SPCR table. As a result of the parsing preferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * console is registered and if @enable_earlycon is true, earlycon is set up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * If @enable_console is true the system console is also configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * When CONFIG_ACPI_SPCR_TABLE is defined, this function should be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * from arch initialization code as soon as the DT/ACPI decision is made.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static char opts[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct acpi_table_spcr *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) char *uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) char *iotype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int baud_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) status = acpi_get_table(ACPI_SIG_SPCR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (struct acpi_table_header **)&table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (table->header.revision < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pr_info("SPCR table version %d\n", table->header.revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (table->serial_port.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) switch (ACPI_ACCESS_BIT_WIDTH((
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) table->serial_port.access_width))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pr_err("Unexpected SPCR Access Width. Defaulting to byte size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) iotype = "mmio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) iotype = "mmio16";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) iotype = "mmio32";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) iotype = "io";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) switch (table->interface_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case ACPI_DBG2_ARM_SBSA_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) iotype = "mmio32";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case ACPI_DBG2_ARM_PL011:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case ACPI_DBG2_ARM_SBSA_GENERIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case ACPI_DBG2_BCM2835:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) uart = "pl011";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case ACPI_DBG2_16550_COMPATIBLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case ACPI_DBG2_16550_SUBSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uart = "uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) switch (table->baud_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * SPCR 1.04 defines 0 as a preconfigured state of UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Assume firmware or bootloader configures console correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) baud_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) baud_rate = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) baud_rate = 19200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) baud_rate = 57600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) baud_rate = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * If the E44 erratum is required, then we need to tell the pl011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * driver to implement the work-around.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * The global variable is used by the probe function when it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * creates the UARTs, whether or not they're used as a console.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * If the user specifies "traditional" earlycon, the qdf2400_e44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * console name matches the EARLYCON_DECLARE() statement, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * SPCR is not used. Parameter "earlycon" is false.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * If the user specifies "SPCR" earlycon, then we need to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * the console name so that it also says "qdf2400_e44". Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * "earlycon" is true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * For consistency, if we change the console name, then we do it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * for everyone, not just earlycon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (qdf2400_erratum_44_present(&table->header)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) qdf2400_e44_present = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (enable_earlycon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uart = "qdf2400_e44";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (xgene_8250_erratum_present(table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) iotype = "mmio32";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* for xgene v1 and v2 we don't know the clock rate of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * UART so don't attempt to change to the baud rate state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * in the table because driver cannot calculate the dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) baud_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!baud_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) table->serial_port.address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) table->serial_port.address, baud_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pr_info("console: %s\n", opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (enable_earlycon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) setup_earlycon(opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (enable_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) err = add_preferred_console(uart, 0, opts + strlen(uart) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) acpi_put_table((struct acpi_table_header *)table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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