Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <acpi/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) static void acpi_pci_reboot(struct acpi_generic_address *rr, u8 reset_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	unsigned int devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	struct pci_bus *bus0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	/* The reset register can only live on bus 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	bus0 = pci_find_bus(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	if (!bus0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	/* Form PCI device/function pair. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	devfn = PCI_DEVFN((rr->address >> 32) & 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			  (rr->address >> 16) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	pr_debug("Resetting with ACPI PCI RESET_REG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	/* Write the value that resets us. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	pci_bus_write_config_byte(bus0, devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			(rr->address & 0xffff), reset_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static inline void acpi_pci_reboot(struct acpi_generic_address *rr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 				   u8 reset_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	pr_warn_once("PCI configuration space access is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void acpi_reboot(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	struct acpi_generic_address *rr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	u8 reset_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	rr = &acpi_gbl_FADT.reset_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	/* ACPI reset register was only introduced with v2 of the FADT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	if (acpi_gbl_FADT.header.revision < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	/* Is the reset register supported? The spec says we should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	 * checking the bit width and bit offset, but Windows ignores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	 * these fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	reset_value = acpi_gbl_FADT.reset_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	/* The reset register can only exist in I/O, Memory or PCI config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	 * on a device on bus 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	switch (rr->space_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	case ACPI_ADR_SPACE_PCI_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		acpi_pci_reboot(rr, reset_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	case ACPI_ADR_SPACE_SYSTEM_MEMORY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	case ACPI_ADR_SPACE_SYSTEM_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		printk(KERN_DEBUG "ACPI MEMORY or I/O RESET_REG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		acpi_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	 * Some platforms do not shut down immediately after writing to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	 * ACPI reset register, and this results in racing with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	 * subsequent reboot mechanism.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	 * The 15ms delay has been found to be long enough for the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	 * to reboot on the affected platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	mdelay(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }