Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * TI TPS68470 PMIC operation region driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Rajmohan Mani <rajmohan.mani@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Based on drivers/acpi/pmic/intel_pmic* drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/tps68470.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct tps68470_pmic_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u32 address;		/* operation region address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	u32 reg;		/* corresponding register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u32 bitmask;		/* bit mask for power, clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TI_PMIC_POWER_OPREGION_ID		0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TI_PMIC_VR_VAL_OPREGION_ID		0xB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TI_PMIC_CLOCK_OPREGION_ID		0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TI_PMIC_CLKFREQ_OPREGION_ID		0xB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct tps68470_pmic_opregion {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define S_IO_I2C_EN	(BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static const struct tps68470_pmic_table power_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.address = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.reg = TPS68470_REG_S_I2C_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.bitmask = S_IO_I2C_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		/* S_I2C_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.address = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.reg = TPS68470_REG_VCMCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.bitmask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		/* VCMCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.address = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.reg = TPS68470_REG_VAUX1CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.bitmask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		/* VAUX1_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.address = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.reg = TPS68470_REG_VAUX2CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.bitmask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		/* VAUX2CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.address = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.reg = TPS68470_REG_VACTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.bitmask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		/* VACTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.address = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.reg = TPS68470_REG_VDCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.bitmask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		/* VDCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* Table to set voltage regulator value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static const struct tps68470_pmic_table vr_val_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.address = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.reg = TPS68470_REG_VSIOVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.bitmask = TPS68470_VSIOVAL_IOVOLT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		/* TPS68470_REG_VSIOVAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.address = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.reg = TPS68470_REG_VIOVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.bitmask = TPS68470_VIOVAL_IOVOLT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		/* TPS68470_REG_VIOVAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.address = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.reg = TPS68470_REG_VCMVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.bitmask = TPS68470_VCMVAL_VCVOLT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		/* TPS68470_REG_VCMVAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.address = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.reg = TPS68470_REG_VAUX1VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.bitmask = TPS68470_VAUX1VAL_AUX1VOLT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		/* TPS68470_REG_VAUX1VAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.address = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.reg = TPS68470_REG_VAUX2VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.bitmask = TPS68470_VAUX2VAL_AUX2VOLT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		/* TPS68470_REG_VAUX2VAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.address = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.reg = TPS68470_REG_VAVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.bitmask = TPS68470_VAVAL_AVOLT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		/* TPS68470_REG_VAVAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.address = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.reg = TPS68470_REG_VDVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.bitmask = TPS68470_VDVAL_DVOLT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		/* TPS68470_REG_VDVAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Table to configure clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct tps68470_pmic_table clk_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		.address = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.reg = TPS68470_REG_POSTDIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.bitmask = BIT(0) | BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		/* TPS68470_REG_POSTDIV2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.address = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.reg = TPS68470_REG_BOOSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.bitmask = 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		/* TPS68470_REG_BOOSTDIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.address = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.reg = TPS68470_REG_BUCKDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.bitmask = 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		/* TPS68470_REG_BUCKDIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.address = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.reg = TPS68470_REG_PLLSWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.bitmask = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		/* TPS68470_REG_PLLSWR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.address = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.reg = TPS68470_REG_XTALDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.bitmask = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		/* TPS68470_REG_XTALDIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.address = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.reg = TPS68470_REG_PLLDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.bitmask = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		/* TPS68470_REG_PLLDIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.address = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.reg = TPS68470_REG_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.bitmask = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		/* TPS68470_REG_POSTDIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Table to configure and enable clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct tps68470_pmic_table clk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.address = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.reg = TPS68470_REG_PLLCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.bitmask = 0xF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		/* TPS68470_REG_PLLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.address = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.reg = TPS68470_REG_PLLCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.bitmask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		/* TPS68470_REG_PLLCTL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.address = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.reg = TPS68470_REG_CLKCFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.bitmask = TPS68470_CLKCFG1_MODE_A_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			TPS68470_CLKCFG1_MODE_B_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		/* TPS68470_REG_CLKCFG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.address = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.reg = TPS68470_REG_CLKCFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.bitmask = TPS68470_CLKCFG1_MODE_A_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			TPS68470_CLKCFG1_MODE_B_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		/* TPS68470_REG_CLKCFG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int pmic_get_reg_bit(u64 address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			    const struct tps68470_pmic_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			    const unsigned int table_size, int *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			    int *bitmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u64 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	i = address / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (i >= table_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (!reg || !bitmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	*reg = table[i].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	*bitmask = table[i].bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int tps68470_pmic_get_power(struct regmap *regmap, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				       int bitmask, u64 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (regmap_read(regmap, reg, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	*value = (data & bitmask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int tps68470_pmic_get_vr_val(struct regmap *regmap, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				       int bitmask, u64 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (regmap_read(regmap, reg, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	*value = data & bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int tps68470_pmic_get_clk(struct regmap *regmap, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				       int bitmask, u64 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (regmap_read(regmap, reg, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	*value = (data & bitmask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int tps68470_pmic_get_clk_freq(struct regmap *regmap, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				       int bitmask, u64 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (regmap_read(regmap, reg, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	*value = data & bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int ti_tps68470_regmap_update_bits(struct regmap *regmap, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 					int bitmask, u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return regmap_update_bits(regmap, reg, bitmask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static acpi_status tps68470_pmic_common_handler(u32 function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 					  acpi_physical_address address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 					  u32 bits, u64 *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 					  void *region_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 					  int (*get)(struct regmap *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 						     int, int, u64 *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 					  int (*update)(struct regmap *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 							int, int, u64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 					  const struct tps68470_pmic_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 					  unsigned int tbl_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct tps68470_pmic_opregion *opregion = region_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct regmap *regmap = opregion->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	int reg, ret, bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (bits != 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		return AE_BAD_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	ret = pmic_get_reg_bit(address, tbl, tbl_size, &reg, &bitmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return AE_BAD_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (function == ACPI_WRITE && *value > bitmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return AE_BAD_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	mutex_lock(&opregion->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	ret = (function == ACPI_READ) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		get(regmap, reg, bitmask, value) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		update(regmap, reg, bitmask, *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	mutex_unlock(&opregion->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return ret ? AE_ERROR : AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static acpi_status tps68470_pmic_cfreq_handler(u32 function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 					    acpi_physical_address address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 					    u32 bits, u64 *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 					    void *handler_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 					    void *region_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	return tps68470_pmic_common_handler(function, address, bits, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 				region_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 				tps68470_pmic_get_clk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				ti_tps68470_regmap_update_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 				clk_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 				ARRAY_SIZE(clk_freq_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static acpi_status tps68470_pmic_clk_handler(u32 function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 				       acpi_physical_address address, u32 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 				       u64 *value, void *handler_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 				       void *region_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return tps68470_pmic_common_handler(function, address, bits, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 				region_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 				tps68470_pmic_get_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 				ti_tps68470_regmap_update_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				clk_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 				ARRAY_SIZE(clk_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static acpi_status tps68470_pmic_vrval_handler(u32 function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 					  acpi_physical_address address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 					  u32 bits, u64 *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 					  void *handler_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 					  void *region_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return tps68470_pmic_common_handler(function, address, bits, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 				region_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 				tps68470_pmic_get_vr_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 				ti_tps68470_regmap_update_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				vr_val_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 				ARRAY_SIZE(vr_val_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static acpi_status tps68470_pmic_pwr_handler(u32 function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 					 acpi_physical_address address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 					 u32 bits, u64 *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 					 void *handler_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 					 void *region_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (bits != 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		return AE_BAD_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	/* set/clear for bit 0, bits 0 and 1 together */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (function == ACPI_WRITE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	    !(*value == 0 || *value == 1 || *value == 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		return AE_BAD_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return tps68470_pmic_common_handler(function, address, bits, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 				region_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 				tps68470_pmic_get_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 				ti_tps68470_regmap_update_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 				power_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 				ARRAY_SIZE(power_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int tps68470_pmic_opregion_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	struct regmap *tps68470_regmap = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	acpi_handle handle = ACPI_HANDLE(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	struct tps68470_pmic_opregion *opregion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (!dev || !tps68470_regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		dev_warn(dev, "dev or regmap is NULL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (!handle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		dev_warn(dev, "acpi handle is NULL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	opregion = devm_kzalloc(dev, sizeof(*opregion), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (!opregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	mutex_init(&opregion->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	opregion->regmap = tps68470_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	status = acpi_install_address_space_handler(handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 						    TI_PMIC_POWER_OPREGION_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 						    tps68470_pmic_pwr_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 						    NULL, opregion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		goto out_mutex_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	status = acpi_install_address_space_handler(handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 						    TI_PMIC_VR_VAL_OPREGION_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 						    tps68470_pmic_vrval_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 						    NULL, opregion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		goto out_remove_power_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	status = acpi_install_address_space_handler(handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 						    TI_PMIC_CLOCK_OPREGION_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 						    tps68470_pmic_clk_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 						    NULL, opregion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		goto out_remove_vr_val_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	status = acpi_install_address_space_handler(handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 						    TI_PMIC_CLKFREQ_OPREGION_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 						    tps68470_pmic_cfreq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 						    NULL, opregion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		goto out_remove_clk_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) out_remove_clk_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	acpi_remove_address_space_handler(handle, TI_PMIC_CLOCK_OPREGION_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 					  tps68470_pmic_clk_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) out_remove_vr_val_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	acpi_remove_address_space_handler(handle, TI_PMIC_VR_VAL_OPREGION_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 					  tps68470_pmic_vrval_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) out_remove_power_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	acpi_remove_address_space_handler(handle, TI_PMIC_POWER_OPREGION_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 					  tps68470_pmic_pwr_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) out_mutex_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	mutex_destroy(&opregion->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct platform_driver tps68470_pmic_opregion_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.probe = tps68470_pmic_opregion_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		.name = "tps68470_pmic_opregion",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) builtin_platform_driver(tps68470_pmic_opregion_driver)