^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NVDIMM Firmware Interface Table - NFIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __NFIT_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __NFIT_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/libnvdimm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ndctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <acpi/acuuid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* ACPI 6.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define UUID_NFIT_BUS "2f10e7a4-9e91-11e4-89d3-123b93f75cba"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* https://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UUID_INTEL_BUS "c7d8acd4-2df8-4b82-9f65-a325335af149"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* https://github.com/HewlettPackard/hpe-nvm/blob/master/Documentation/ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UUID_NFIT_DIMM_N_HPE1 "9002c334-acf3-4c0e-9642-a235f0d53bc6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UUID_NFIT_DIMM_N_HPE2 "5008664b-b758-41a0-a03c-27c2f2d04f7e"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* https://msdn.microsoft.com/library/windows/hardware/mt604741 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UUID_NFIT_DIMM_N_MSFT "1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* http://www.uefi.org/RFIC_LIST (see "Virtual NVDIMM 0x1901") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UUID_NFIT_DIMM_N_HYPERV "5746c5f2-a9a2-4264-ad0e-e4ddc9e09e80"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ACPI_NFIT_MEM_FAILED_MASK (ACPI_NFIT_MEM_SAVE_FAILED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) | ACPI_NFIT_MEM_RESTORE_FAILED | ACPI_NFIT_MEM_FLUSH_FAILED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) | ACPI_NFIT_MEM_NOT_ARMED | ACPI_NFIT_MEM_MAP_FAILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NVDIMM_CMD_MAX 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NVDIMM_STANDARD_CMDMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (1 << ND_CMD_SMART | 1 << ND_CMD_SMART_THRESHOLD | 1 << ND_CMD_DIMM_FLAGS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) | 1 << ND_CMD_GET_CONFIG_SIZE | 1 << ND_CMD_GET_CONFIG_DATA \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) | 1 << ND_CMD_SET_CONFIG_DATA | 1 << ND_CMD_VENDOR_EFFECT_LOG_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) | 1 << ND_CMD_VENDOR_EFFECT_LOG | 1 << ND_CMD_VENDOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Command numbers that the kernel needs to know about to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * non-default DSM revision ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum nvdimm_family_cmds {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) NVDIMM_INTEL_LATCH_SHUTDOWN = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) NVDIMM_INTEL_GET_MODES = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) NVDIMM_INTEL_GET_FWINFO = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) NVDIMM_INTEL_START_FWUPDATE = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) NVDIMM_INTEL_SEND_FWUPDATE = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) NVDIMM_INTEL_FINISH_FWUPDATE = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) NVDIMM_INTEL_QUERY_FWUPDATE = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) NVDIMM_INTEL_SET_THRESHOLD = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) NVDIMM_INTEL_INJECT_ERROR = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) NVDIMM_INTEL_GET_SECURITY_STATE = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) NVDIMM_INTEL_SET_PASSPHRASE = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) NVDIMM_INTEL_DISABLE_PASSPHRASE = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) NVDIMM_INTEL_UNLOCK_UNIT = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) NVDIMM_INTEL_FREEZE_LOCK = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) NVDIMM_INTEL_SECURE_ERASE = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) NVDIMM_INTEL_OVERWRITE = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) NVDIMM_INTEL_QUERY_OVERWRITE = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) NVDIMM_INTEL_SET_MASTER_PASSPHRASE = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) NVDIMM_INTEL_MASTER_SECURE_ERASE = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) NVDIMM_INTEL_FW_ACTIVATE_ARM = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enum nvdimm_bus_family_cmds {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) NVDIMM_BUS_INTEL_FW_ACTIVATE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define NVDIMM_INTEL_SECURITY_CMDMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) (1 << NVDIMM_INTEL_GET_SECURITY_STATE | 1 << NVDIMM_INTEL_SET_PASSPHRASE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) | 1 << NVDIMM_INTEL_DISABLE_PASSPHRASE | 1 << NVDIMM_INTEL_UNLOCK_UNIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) | 1 << NVDIMM_INTEL_FREEZE_LOCK | 1 << NVDIMM_INTEL_SECURE_ERASE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) | 1 << NVDIMM_INTEL_OVERWRITE | 1 << NVDIMM_INTEL_QUERY_OVERWRITE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) | 1 << NVDIMM_INTEL_SET_MASTER_PASSPHRASE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) | 1 << NVDIMM_INTEL_MASTER_SECURE_ERASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define NVDIMM_INTEL_FW_ACTIVATE_CMDMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (1 << NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO | 1 << NVDIMM_INTEL_FW_ACTIVATE_ARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NVDIMM_BUS_INTEL_FW_ACTIVATE_CMDMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) (1 << NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO | 1 << NVDIMM_BUS_INTEL_FW_ACTIVATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define NVDIMM_INTEL_CMDMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) (NVDIMM_STANDARD_CMDMASK | 1 << NVDIMM_INTEL_GET_MODES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) | 1 << NVDIMM_INTEL_GET_FWINFO | 1 << NVDIMM_INTEL_START_FWUPDATE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) | 1 << NVDIMM_INTEL_SEND_FWUPDATE | 1 << NVDIMM_INTEL_FINISH_FWUPDATE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) | 1 << NVDIMM_INTEL_QUERY_FWUPDATE | 1 << NVDIMM_INTEL_SET_THRESHOLD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) | 1 << NVDIMM_INTEL_INJECT_ERROR | 1 << NVDIMM_INTEL_LATCH_SHUTDOWN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) | NVDIMM_INTEL_SECURITY_CMDMASK | NVDIMM_INTEL_FW_ACTIVATE_CMDMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define NVDIMM_INTEL_DENY_CMDMASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (NVDIMM_INTEL_SECURITY_CMDMASK | NVDIMM_INTEL_FW_ACTIVATE_CMDMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum nfit_uuids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* for simplicity alias the uuid index with the family id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) NFIT_DEV_DIMM = NVDIMM_FAMILY_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) NFIT_DEV_DIMM_N_HPE1 = NVDIMM_FAMILY_HPE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) NFIT_DEV_DIMM_N_HPE2 = NVDIMM_FAMILY_HPE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) NFIT_DEV_DIMM_N_MSFT = NVDIMM_FAMILY_MSFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) NFIT_DEV_DIMM_N_HYPERV = NVDIMM_FAMILY_HYPERV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * to_nfit_bus_uuid() expects to translate bus uuid family ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * to a UUID index using NVDIMM_FAMILY_MAX as an offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) NFIT_BUS_INTEL = NVDIMM_FAMILY_MAX + NVDIMM_BUS_FAMILY_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) NFIT_SPA_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) NFIT_SPA_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) NFIT_SPA_DCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) NFIT_SPA_BDW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) NFIT_SPA_VDISK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) NFIT_SPA_VCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) NFIT_SPA_PDISK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) NFIT_SPA_PCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) NFIT_DEV_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) NFIT_UUID_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Region format interface codes are stored with the interface as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * LSB and the function as the MSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define NFIT_FIC_BYTE cpu_to_le16(0x101) /* byte-addressable energy backed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define NFIT_FIC_BLK cpu_to_le16(0x201) /* block-addressable non-energy backed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define NFIT_FIC_BYTEN cpu_to_le16(0x301) /* byte-addressable non-energy backed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) NFIT_BLK_READ_FLUSH = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) NFIT_BLK_DCR_LATCH = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) NFIT_ARS_STATUS_DONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) NFIT_ARS_STATUS_BUSY = 1 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) NFIT_ARS_STATUS_NONE = 2 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) NFIT_ARS_STATUS_INTR = 3 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) NFIT_ARS_START_BUSY = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) NFIT_ARS_CAP_NONE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) NFIT_ARS_F_OVERFLOW = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) NFIT_ARS_TIMEOUT = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum nfit_root_notifiers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) NFIT_NOTIFY_UPDATE = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) NFIT_NOTIFY_UC_MEMORY_ERROR = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum nfit_dimm_notifiers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) NFIT_NOTIFY_DIMM_HEALTH = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) enum nfit_ars_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ARS_REQ_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ARS_REQ_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ARS_FAILED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct nfit_spa {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct nd_region *nd_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long ars_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 clear_err_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 max_ars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct acpi_nfit_system_address spa[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct nfit_dcr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct acpi_nfit_control_region dcr[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct nfit_bdw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct acpi_nfit_data_region bdw[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct nfit_idt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct acpi_nfit_interleave idt[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct nfit_flush {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct acpi_nfit_flush_address flush[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct nfit_memdev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct acpi_nfit_memory_map memdev[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) enum nfit_mem_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) NFIT_MEM_LSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) NFIT_MEM_LSW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) NFIT_MEM_DIRTY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) NFIT_MEM_DIRTY_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define NFIT_DIMM_ID_LEN 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* assembled tables for a given dimm/memory-device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct nfit_mem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct nvdimm *nvdimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct acpi_nfit_memory_map *memdev_dcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct acpi_nfit_memory_map *memdev_pmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct acpi_nfit_memory_map *memdev_bdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct acpi_nfit_control_region *dcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct acpi_nfit_data_region *bdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct acpi_nfit_system_address *spa_dcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct acpi_nfit_system_address *spa_bdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct acpi_nfit_interleave *idt_dcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct acpi_nfit_interleave *idt_bdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct kernfs_node *flags_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct nfit_flush *nfit_flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct acpi_nfit_desc *acpi_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) enum nvdimm_fwa_state fwa_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum nvdimm_fwa_result fwa_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int fwa_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) char id[NFIT_DIMM_ID_LEN+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct resource *flush_wpq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long dsm_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 dirty_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) enum scrub_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ARS_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ARS_CANCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ARS_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ARS_POLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct acpi_nfit_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct nvdimm_bus_descriptor nd_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct acpi_table_header acpi_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct mutex init_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct list_head memdevs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct list_head flushes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct list_head dimms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct list_head spas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct list_head dcrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct list_head bdws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct list_head idts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct nvdimm_bus *nvdimm_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct nd_cmd_ars_status *ars_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct nfit_spa *scrub_spa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct delayed_work dwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct kernfs_node *scrub_count_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int max_ars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int scrub_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int scrub_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long scrub_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned long dimm_cmd_force_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long bus_cmd_force_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long bus_dsm_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long family_dsm_mask[NVDIMM_BUS_FAMILY_MAX + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int platform_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int scrub_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int (*blk_do_io)(struct nd_blk_region *ndbr, resource_size_t dpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void *iobuf, u64 len, int rw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) enum nvdimm_fwa_state fwa_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) enum nvdimm_fwa_capability fwa_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int fwa_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bool fwa_noidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) bool fwa_nosuspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) enum scrub_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) HW_ERROR_SCRUB_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) HW_ERROR_SCRUB_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) enum nd_blk_mmio_selector {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) BDW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct nd_blk_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void *aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct nfit_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct nfit_blk_mmio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct nd_blk_addr addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u64 base_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 num_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct acpi_nfit_interleave *idt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct acpi_nfit_system_address *spa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } mmio[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct nd_region *nd_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u64 bdw_offset; /* post interleave offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u64 stat_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u64 cmd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 dimm_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) extern struct list_head acpi_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) extern struct mutex acpi_desc_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int acpi_nfit_ars_rescan(struct acpi_nfit_desc *acpi_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) enum nfit_ars_state req_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #ifdef CONFIG_X86_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void nfit_mce_register(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void nfit_mce_unregister(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static inline void nfit_mce_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static inline void nfit_mce_unregister(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int nfit_spa_type(struct acpi_nfit_system_address *spa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static inline struct acpi_nfit_memory_map *__to_nfit_memdev(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct nfit_mem *nfit_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (nfit_mem->memdev_dcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return nfit_mem->memdev_dcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return nfit_mem->memdev_pmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static inline struct acpi_nfit_desc *to_acpi_desc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct nvdimm_bus_descriptor *nd_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return container_of(nd_desc, struct acpi_nfit_desc, nd_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #ifdef CONFIG_PROVE_LOCKING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static inline void nfit_device_lock(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) device_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mutex_lock(&dev->lockdep_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static inline void nfit_device_unlock(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mutex_unlock(&dev->lockdep_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) device_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static inline void nfit_device_lock(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) device_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static inline void nfit_device_unlock(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) device_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) const guid_t *to_nfit_uuid(enum nfit_uuids id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, void *nfit, acpi_size sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void acpi_nfit_shutdown(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void __acpi_nfit_notify(struct device *dev, acpi_handle handle, u32 event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) void __acpi_nvdimm_notify(struct device *dev, u32 event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int acpi_nfit_ctl(struct nvdimm_bus_descriptor *nd_desc, struct nvdimm *nvdimm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int cmd, void *buf, unsigned int buf_len, int *cmd_rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) void acpi_nfit_desc_init(struct acpi_nfit_desc *acpi_desc, struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bool intel_fwa_supported(struct nvdimm_bus *nvdimm_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) extern struct device_attribute dev_attr_firmware_activate_noidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif /* __NFIT_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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