^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Intel specific definitions for NVDIMM Firmware Interface Table - NFIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _NFIT_INTEL_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _NFIT_INTEL_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ND_INTEL_SMART 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ND_INTEL_SMART_SHUTDOWN_COUNT_VALID (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ND_INTEL_SMART_SHUTDOWN_VALID (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct nd_intel_smart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 reserved0[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 health;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 spares;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u8 life_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 alarm_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u16 media_temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u16 ctrl_temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 shutdown_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 ait_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u16 pmic_temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 reserved1[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 shutdown_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 vendor_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 vendor_data[92];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 data[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern const struct nvdimm_security_ops *intel_security_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ND_INTEL_STATUS_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ND_INTEL_PASSPHRASE_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ND_INTEL_STATUS_NOT_SUPPORTED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ND_INTEL_STATUS_RETRY 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ND_INTEL_STATUS_NOT_READY 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ND_INTEL_STATUS_INVALID_STATE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ND_INTEL_STATUS_INVALID_PASS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ND_INTEL_STATUS_OVERWRITE_UNSUPPORTED 0x10007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ND_INTEL_STATUS_OQUERY_INPROGRESS 0x10007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR 0x20007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ND_INTEL_SEC_STATE_ENABLED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ND_INTEL_SEC_STATE_LOCKED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ND_INTEL_SEC_STATE_FROZEN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ND_INTEL_SEC_STATE_PLIMIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ND_INTEL_SEC_STATE_UNSUPPORTED 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ND_INTEL_SEC_STATE_OVERWRITE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ND_INTEL_SEC_ESTATE_ENABLED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ND_INTEL_SEC_ESTATE_PLIMIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct nd_intel_get_security_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 extended_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 reserved1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct nd_intel_set_passphrase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct nd_intel_unlock_unit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct nd_intel_disable_passphrase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct nd_intel_freeze_lock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct nd_intel_secure_erase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct nd_intel_overwrite {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct nd_intel_query_overwrite {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct nd_intel_set_master_passphrase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct nd_intel_master_secure_erase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ND_INTEL_FWA_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ND_INTEL_FWA_ARMED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ND_INTEL_FWA_BUSY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ND_INTEL_DIMM_FWA_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ND_INTEL_DIMM_FWA_NOTSTAGED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ND_INTEL_DIMM_FWA_SUCCESS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ND_INTEL_DIMM_FWA_NEEDRESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ND_INTEL_DIMM_FWA_MEDIAFAILED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ND_INTEL_DIMM_FWA_ABORT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ND_INTEL_DIMM_FWA_NOTSUPP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ND_INTEL_DIMM_FWA_ERROR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct nd_intel_fw_activate_dimminfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 reserved[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ND_INTEL_DIMM_FWA_ARM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ND_INTEL_DIMM_FWA_DISARM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct nd_intel_fw_activate_arm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 activate_arm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Root device command payloads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ND_INTEL_BUS_FWA_CAP_FWQUIESCE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ND_INTEL_BUS_FWA_CAP_OSQUIESCE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ND_INTEL_BUS_FWA_CAP_RESET (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct nd_intel_bus_fw_activate_businfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u64 activate_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u64 cpu_quiesce_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u64 io_quiesce_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u64 max_quiesce_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ND_INTEL_BUS_FWA_STATUS_NOARM (6 | 1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ND_INTEL_BUS_FWA_STATUS_BUSY (6 | 2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ND_INTEL_BUS_FWA_STATUS_NOFW (6 | 3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ND_INTEL_BUS_FWA_STATUS_TMO (6 | 4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ND_INTEL_BUS_FWA_STATUS_NOIDLE (6 | 5 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ND_INTEL_BUS_FWA_STATUS_ABORT (6 | 6 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ND_INTEL_BUS_FWA_IODEV_FORCE_IDLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ND_INTEL_BUS_FWA_IODEV_OS_IDLE (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct nd_intel_bus_fw_activate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 iodev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) extern const struct nvdimm_fw_ops *intel_fw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) extern const struct nvdimm_bus_fw_ops *intel_bus_fw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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