Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Module Name: rsirq - IRQ resource descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <acpi/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include "accommon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "acresrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define _COMPONENT          ACPI_RESOURCES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) ACPI_MODULE_NAME("rsirq")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /*******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * acpi_rs_get_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) struct acpi_rsconvert_info acpi_rs_get_irq[9] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	{ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	 ACPI_RS_SIZE(struct acpi_resource_irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	 ACPI_RSC_TABLE_SIZE(acpi_rs_get_irq)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	/* Get the IRQ mask (bytes 1:2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	{ACPI_RSC_BITMASK16, ACPI_RS_OFFSET(data.irq.interrupts[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	 AML_OFFSET(irq.irq_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	 ACPI_RS_OFFSET(data.irq.interrupt_count)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	/* Set default flags (others are zero) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{ACPI_RSC_SET8, ACPI_RS_OFFSET(data.irq.triggering),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	 ACPI_EDGE_SENSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	/* Get the descriptor length (2 or 3 for IRQ descriptor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{ACPI_RSC_2BITFLAG, ACPI_RS_OFFSET(data.irq.descriptor_length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	 AML_OFFSET(irq.descriptor_type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/* All done if no flag byte present in descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{ACPI_RSC_EXIT_NE, ACPI_RSC_COMPARE_AML_LENGTH, 0, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/* Get flags: Triggering[0], Polarity[3], Sharing[4], Wake[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.irq.triggering),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	 AML_OFFSET(irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.irq.polarity),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 AML_OFFSET(irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.irq.shareable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 AML_OFFSET(irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.irq.wake_capable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 AML_OFFSET(irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 5}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /*******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * acpi_rs_set_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) struct acpi_rsconvert_info acpi_rs_set_irq[14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* Start with a default descriptor of length 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 sizeof(struct aml_resource_irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 ACPI_RSC_TABLE_SIZE(acpi_rs_set_irq)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* Convert interrupt list to 16-bit IRQ bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{ACPI_RSC_BITMASK16, ACPI_RS_OFFSET(data.irq.interrupts[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 AML_OFFSET(irq.irq_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 ACPI_RS_OFFSET(data.irq.interrupt_count)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* Set flags: Triggering[0], Polarity[3], Sharing[4], Wake[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.irq.triggering),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 AML_OFFSET(irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.irq.polarity),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 AML_OFFSET(irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.irq.shareable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 AML_OFFSET(irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.irq.wake_capable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 AML_OFFSET(irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * All done if the output descriptor length is required to be 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * (i.e., optimization to 2 bytes cannot be attempted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{ACPI_RSC_EXIT_EQ, ACPI_RSC_COMPARE_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 ACPI_RS_OFFSET(data.irq.descriptor_length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* Set length to 2 bytes (no flags byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{ACPI_RSC_LENGTH, 0, 0, sizeof(struct aml_resource_irq_noflags)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * All done if the output descriptor length is required to be 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * TBD: Perhaps we should check for error if input flags are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * compatible with a 2-byte descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{ACPI_RSC_EXIT_EQ, ACPI_RSC_COMPARE_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 ACPI_RS_OFFSET(data.irq.descriptor_length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* Reset length to 3 bytes (descriptor with flags byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ACPI_RSC_LENGTH, 0, 0, sizeof(struct aml_resource_irq)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * Check if the flags byte is necessary. Not needed if the flags are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_HIGH, ACPI_EXCLUSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{ACPI_RSC_EXIT_NE, ACPI_RSC_COMPARE_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 ACPI_RS_OFFSET(data.irq.triggering),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 ACPI_EDGE_SENSITIVE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{ACPI_RSC_EXIT_NE, ACPI_RSC_COMPARE_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 ACPI_RS_OFFSET(data.irq.polarity),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 ACPI_ACTIVE_HIGH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{ACPI_RSC_EXIT_NE, ACPI_RSC_COMPARE_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 ACPI_RS_OFFSET(data.irq.shareable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 ACPI_EXCLUSIVE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/* We can optimize to a 2-byte irq_no_flags() descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{ACPI_RSC_LENGTH, 0, 0, sizeof(struct aml_resource_irq_noflags)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * acpi_rs_convert_ext_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct acpi_rsconvert_info acpi_rs_convert_ext_irq[10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_EXTENDED_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 ACPI_RS_SIZE(struct acpi_resource_extended_irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 ACPI_RSC_TABLE_SIZE(acpi_rs_convert_ext_irq)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	{ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_EXTENDED_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 sizeof(struct aml_resource_extended_irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 * Flags: Producer/Consumer[0], Triggering[1], Polarity[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 *        Sharing[3], Wake[4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.extended_irq.producer_consumer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	 AML_OFFSET(extended_irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.extended_irq.triggering),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	 AML_OFFSET(extended_irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.extended_irq.polarity),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 AML_OFFSET(extended_irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.extended_irq.shareable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 AML_OFFSET(extended_irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.extended_irq.wake_capable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 AML_OFFSET(extended_irq.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* IRQ Table length (Byte4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{ACPI_RSC_COUNT, ACPI_RS_OFFSET(data.extended_irq.interrupt_count),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 AML_OFFSET(extended_irq.interrupt_count),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 sizeof(u32)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* Copy every IRQ in the table, each is 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{ACPI_RSC_MOVE32, ACPI_RS_OFFSET(data.extended_irq.interrupts[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 AML_OFFSET(extended_irq.interrupts[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/* Optional resource_source (Index and String) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	{ACPI_RSC_SOURCEX, ACPI_RS_OFFSET(data.extended_irq.resource_source),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 ACPI_RS_OFFSET(data.extended_irq.interrupts[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 sizeof(struct aml_resource_extended_irq)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * acpi_rs_convert_dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct acpi_rsconvert_info acpi_rs_convert_dma[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	{ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 ACPI_RS_SIZE(struct acpi_resource_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 ACPI_RSC_TABLE_SIZE(acpi_rs_convert_dma)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	{ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 sizeof(struct aml_resource_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* Flags: transfer preference, bus mastering, channel speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	{ACPI_RSC_2BITFLAG, ACPI_RS_OFFSET(data.dma.transfer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 AML_OFFSET(dma.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.dma.bus_master),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 AML_OFFSET(dma.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{ACPI_RSC_2BITFLAG, ACPI_RS_OFFSET(data.dma.type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 AML_OFFSET(dma.flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* DMA channel mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	{ACPI_RSC_BITMASK, ACPI_RS_OFFSET(data.dma.channels[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 AML_OFFSET(dma.dma_channel_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 ACPI_RS_OFFSET(data.dma.channel_count)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  * acpi_rs_convert_fixed_dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct acpi_rsconvert_info acpi_rs_convert_fixed_dma[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	{ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_FIXED_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 ACPI_RS_SIZE(struct acpi_resource_fixed_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 ACPI_RSC_TABLE_SIZE(acpi_rs_convert_fixed_dma)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	{ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_FIXED_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 sizeof(struct aml_resource_fixed_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 * These fields are contiguous in both the source and destination:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 * request_lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * Channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	{ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.fixed_dma.request_lines),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 AML_OFFSET(fixed_dma.request_lines),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	{ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.fixed_dma.width),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	 AML_OFFSET(fixed_dma.width),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };