^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ACPI support for Intel Lynxpoint LPSS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_data/x86/clk-lpss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/x86/pmc_atom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifdef CONFIG_X86_INTEL_LPSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/cpu_device_id.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/intel-family.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/iosf_mbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPSS_ADDR(desc) ((unsigned long)&desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPSS_CLK_SIZE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPSS_LTR_SIZE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Offsets relative to LPSS_PRIVATE_OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPSS_RESETS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPSS_RESETS_RESET_FUNC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPSS_RESETS_RESET_APB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LPSS_GENERAL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LPSS_SW_LTR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LPSS_AUTO_LTR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LPSS_LTR_SNOOP_REQ BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LPSS_LTR_SNOOP_LAT_1US 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LPSS_LTR_SNOOP_LAT_32US 0xC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LPSS_LTR_SNOOP_LAT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LPSS_LTR_MAX_VAL 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LPSS_TX_INT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LPSS_TX_INT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LPSS_PRV_REG_COUNT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* LPSS Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LPSS_CLK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LPSS_CLK_GATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LPSS_CLK_DIVIDER BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LPSS_LTR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LPSS_SAVE_CTX BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * For some devices the DSDT AML code for another device turns off the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * as ctx register values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Luckily these devices always use the same ctx register values, so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * work around this by saving the ctx registers once on activation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LPSS_SAVE_CTX_ONCE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LPSS_NO_D3_DELAY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct lpss_private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct lpss_device_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char *clk_con_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int prv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) size_t prv_size_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct property_entry *properties;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void (*setup)(struct lpss_private_data *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bool resume_from_noirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct lpss_device_desc lpss_dma_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .flags = LPSS_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct lpss_private_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) resource_size_t mmio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int fixed_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const struct lpss_device_desc *dev_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static u32 pmc_atom_d3_mask = 0xfe000ffe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* LPSS run time quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static unsigned int lpss_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * it can be powered off automatically whenever the last LPSS device goes down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * In case of no power any access to the DMA controller will hang the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * well as on ASuS T100TA transformer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * This quirk overrides power state of entire LPSS island to keep DMA powered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * on whenever we have at least one other device in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* UART Component Parameter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LPSS_UART_CPR 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LPSS_UART_CPR_AFCE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void lpss_uart_setup(struct lpss_private_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) val = readl(pdata->mmio_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) val = readl(pdata->mmio_base + LPSS_UART_CPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (!(val & LPSS_UART_CPR_AFCE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) val = readl(pdata->mmio_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val |= LPSS_GENERAL_UART_RTS_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(val, pdata->mmio_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void lpss_deassert_reset(struct lpss_private_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val = readl(pdata->mmio_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel(val, pdata->mmio_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * BYT PWM used for backlight control by the i915 driver on systems without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * the Crystal Cove PMIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct pwm_lookup byt_pwm_lookup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "pwm-lpss-platform"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void byt_pwm_setup(struct lpss_private_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct acpi_device *adev = pdata->adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Only call pwm_add_table for the first PWM controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LPSS_I2C_ENABLE 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void byt_i2c_setup(struct lpss_private_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const char *uid_str = acpi_device_uid(pdata->adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) acpi_handle handle = pdata->adev->handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long long shared_host = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) long uid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Expected to always be true, but better safe then sorry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (uid_str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) uid = simple_strtol(uid_str, NULL, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Detect I2C bus shared with PUNIT and ignore its d3 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ACPI_SUCCESS(status) && shared_host && uid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) lpss_deassert_reset(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pdata->fixed_clk_rate = 133000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* BSW PWM used for backlight control by the i915 driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static struct pwm_lookup bsw_pwm_lookup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "pwm-lpss-platform"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void bsw_pwm_setup(struct lpss_private_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct acpi_device *adev = pdata->adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Only call pwm_add_table for the first PWM controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct lpss_device_desc lpt_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) | LPSS_SAVE_CTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .prv_offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct lpss_device_desc lpt_i2c_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .prv_offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct property_entry uart_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PROPERTY_ENTRY_U32("reg-io-width", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PROPERTY_ENTRY_U32("reg-shift", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct lpss_device_desc lpt_uart_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) | LPSS_SAVE_CTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .clk_con_id = "baudclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .prv_offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .setup = lpss_uart_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .properties = uart_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct lpss_device_desc lpt_sdio_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .flags = LPSS_LTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .prv_offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .prv_size_override = 0x1018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct lpss_device_desc byt_pwm_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .flags = LPSS_SAVE_CTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .prv_offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .setup = byt_pwm_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct lpss_device_desc bsw_pwm_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .prv_offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .setup = bsw_pwm_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .resume_from_noirq = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct lpss_device_desc byt_uart_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .clk_con_id = "baudclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .prv_offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .setup = lpss_uart_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .properties = uart_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct lpss_device_desc bsw_uart_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) | LPSS_NO_D3_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .clk_con_id = "baudclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .prv_offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .setup = lpss_uart_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .properties = uart_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct lpss_device_desc byt_spi_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .prv_offset = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct lpss_device_desc byt_sdio_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .flags = LPSS_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct lpss_device_desc byt_i2c_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .flags = LPSS_CLK | LPSS_SAVE_CTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .prv_offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .setup = byt_i2c_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .resume_from_noirq = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct lpss_device_desc bsw_i2c_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .prv_offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .setup = byt_i2c_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .resume_from_noirq = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const struct lpss_device_desc bsw_spi_dev_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) | LPSS_NO_D3_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .prv_offset = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .setup = lpss_deassert_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct x86_cpu_id lpss_cpu_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define LPSS_ADDR(desc) (0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #endif /* CONFIG_X86_INTEL_LPSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const struct acpi_device_id acpi_lpss_device_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Generic LPSS devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Lynxpoint LPSS devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { "INT33C7", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* BayTrail LPSS devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { "INT33B2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { "INT33FC", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Braswell LPSS devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { "80862286", LPSS_ADDR(lpss_dma_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { "808622C0", LPSS_ADDR(lpss_dma_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Broadwell LPSS devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { "INT3430", LPSS_ADDR(lpt_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { "INT3431", LPSS_ADDR(lpt_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { "INT3437", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Wildcat Point LPSS devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { "INT3438", LPSS_ADDR(lpt_dev_desc) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #ifdef CONFIG_X86_INTEL_LPSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int is_memory(struct acpi_resource *res, void *not_used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return !acpi_dev_resource_memory(res, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* LPSS main clock device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct platform_device *lpss_clk_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static inline void lpt_register_clock_device(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int register_device_clock(struct acpi_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct lpss_private_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) const struct lpss_device_desc *dev_desc = pdata->dev_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) const char *devname = dev_name(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct lpss_clk_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const char *parent, *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void __iomem *prv_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!lpss_clk_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) lpt_register_clock_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) clk_data = platform_get_drvdata(lpss_clk_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) clk = clk_data->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!pdata->mmio_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) parent = clk_data->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) prv_base = pdata->mmio_base + dev_desc->prv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (pdata->fixed_clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clk = clk_register_fixed_rate(NULL, devname, parent, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) pdata->fixed_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (dev_desc->flags & LPSS_CLK_GATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clk = clk_register_gate(NULL, devname, parent, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) prv_base, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) parent = devname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (dev_desc->flags & LPSS_CLK_DIVIDER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Prevent division by zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!readl(prv_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!clk_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) clk = clk_register_fractional_divider(NULL, clk_name, parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0, prv_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 1, 15, 16, 15, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) parent = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!clk_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) kfree(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) clk = clk_register_gate(NULL, clk_name, parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) prv_base, 31, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) kfree(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) kfree(clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pdata->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct lpss_device_links {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) const char *supplier_hid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) const char *supplier_uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) const char *consumer_hid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) const char *consumer_uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) const struct dmi_system_id *dep_missing_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Please keep this list sorted alphabetically by vendor and model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * The _DEP method is used to identify dependencies but instead of creating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * device links for every handle in _DEP, only links in the following list are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * created. That is necessary because, in the general case, _DEP can refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * devices that might not have drivers, or that are on different buses, or where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * the supplier is not enumerated until after the consumer is probed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const struct lpss_device_links lpss_device_links[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* CHT External sdcard slot controller depends on PMIC I2C ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* CHT iGPU depends on PMIC I2C controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) i2c1_dep_missing_dmi_ids},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static bool acpi_lpss_is_supplier(struct acpi_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) const struct lpss_device_links *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static bool acpi_lpss_is_consumer(struct acpi_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) const struct lpss_device_links *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct hid_uid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) const char *hid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) const char *uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int match_hid_uid(struct device *dev, const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct acpi_device *adev = ACPI_COMPANION(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) const struct hid_uid *id = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct hid_uid data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .hid = hid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .uid = uid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct acpi_handle_list dep_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!acpi_has_method(adev->handle, "_DEP"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) &dep_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ACPI_FAILURE(status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) for (i = 0; i < dep_devices.count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (dep_devices.handles[i] == handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void acpi_lpss_link_consumer(struct device *dev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) const struct lpss_device_links *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct device *dev2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!dev2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) device_link_add(dev2, dev1, link->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) put_device(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void acpi_lpss_link_supplier(struct device *dev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) const struct lpss_device_links *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct device *dev2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!dev2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) device_link_add(dev1, dev2, link->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) put_device(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void acpi_lpss_create_device_links(struct acpi_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) const struct lpss_device_links *link = &lpss_device_links[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (acpi_lpss_is_supplier(adev, link))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) acpi_lpss_link_consumer(&pdev->dev, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (acpi_lpss_is_consumer(adev, link))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) acpi_lpss_link_supplier(&pdev->dev, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int acpi_lpss_create_device(struct acpi_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) const struct acpi_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) const struct lpss_device_desc *dev_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct lpss_private_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct resource_entry *rentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct list_head resource_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_desc = (const struct lpss_device_desc *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!dev_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pdev = acpi_create_platform_device(adev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) INIT_LIST_HEAD(&resource_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) list_for_each_entry(rentry, &resource_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (resource_type(rentry->res) == IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (dev_desc->prv_size_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pdata->mmio_size = dev_desc->prv_size_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pdata->mmio_size = resource_size(rentry->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pdata->mmio_base = ioremap(rentry->res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pdata->mmio_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) acpi_dev_free_resource_list(&resource_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (!pdata->mmio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) adev->pnp.type.platform_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Skip the device, but continue the namespace scan. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pdata->adev = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pdata->dev_desc = dev_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (dev_desc->setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_desc->setup(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (dev_desc->flags & LPSS_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = register_device_clock(adev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Skip the device, but continue the namespace scan. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * This works around a known issue in ACPI tables where LPSS devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * have _PS0 and _PS3 without _PSC (and no power resources), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * acpi_bus_init_power() will assume that the BIOS has put them into D0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) acpi_device_fix_up_power(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) adev->driver_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pdev = acpi_create_platform_device(adev, dev_desc->properties);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (!IS_ERR_OR_NULL(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) acpi_lpss_create_device_links(adev, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = PTR_ERR(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) adev->driver_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) kfree(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct lpss_private_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) spin_lock_irqsave(&dev->power.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (pm_runtime_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pdata = acpi_driver_data(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (WARN_ON(!pdata || !pdata->mmio_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) *val = __lpss_reg_read(pdata, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) spin_unlock_irqrestore(&dev->power.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 ltr_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = lpss_reg_read(dev, reg, <r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static ssize_t lpss_ltr_mode_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u32 ltr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) char *outstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return sprintf(buf, "%s\n", outstr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static struct attribute *lpss_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) &dev_attr_auto_ltr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) &dev_attr_sw_ltr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) &dev_attr_ltr_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const struct attribute_group lpss_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .attrs = lpss_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .name = "lpss_ltr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void acpi_lpss_set_ltr(struct device *dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 ltr_mode, ltr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) val = LPSS_LTR_MAX_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) } else if (val > LPSS_LTR_MAX_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ltr_val |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * acpi_lpss_save_ctx() - Save the private registers of LPSS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * @dev: LPSS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * @pdata: pointer to the private data of the LPSS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * Most LPSS devices have private registers which may loose their context when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * the device is powered down. acpi_lpss_save_ctx() saves those registers into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * prv_reg_ctx array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static void acpi_lpss_save_ctx(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct lpss_private_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) unsigned long offset = i * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) pdata->prv_reg_ctx[i], offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * @dev: LPSS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * @pdata: pointer to the private data of the LPSS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * Restores the registers that were previously stored with acpi_lpss_save_ctx().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static void acpi_lpss_restore_ctx(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct lpss_private_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) unsigned long offset = i * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pdata->prv_reg_ctx[i], offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * The following delay is needed or the subsequent write operations may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * fail. The LPSS devices are actually PCI devices and the PCI spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * expects 10ms delay before the device can be accessed after D3 to D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * transition. However some platforms like BSW does not need this delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned int delay = 10; /* default 10ms delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) msleep(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int acpi_lpss_activate(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ret = acpi_dev_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) acpi_lpss_d3_to_d0_delay(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * This is called only on ->probe() stage where a device is either in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * known state defined by BIOS or most likely powered off. Due to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * we have to deassert reset line to be sure that ->probe() will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * recognize the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) lpss_deassert_reset(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) acpi_lpss_save_ctx(dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static void acpi_lpss_dismiss(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) acpi_dev_suspend(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* IOSF SB for LPSS island */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define LPSS_IOSF_UNIT_LPIOEP 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define LPSS_IOSF_UNIT_LPIO1 0xAB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define LPSS_IOSF_UNIT_LPIO2 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define LPSS_IOSF_PMCSR 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define LPSS_PMCSR_D0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define LPSS_PMCSR_D3hot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define LPSS_IOSF_GPIODEF0 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define LPSS_GPIODEF0_DMA_LLP BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static DEFINE_MUTEX(lpss_iosf_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static bool lpss_iosf_d3_entered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static void lpss_iosf_enter_d3_state(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u32 value1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) u32 value2 = LPSS_PMCSR_D3hot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u32 mask2 = LPSS_PMCSR_Dx_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * PMC provides an information about actual status of the LPSS devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * Here we read the values related to LPSS power island, i.e. LPSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * devices, excluding both LPSS DMA controllers, along with SCC domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u32 func_dis, d3_sts_0, pmc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) mutex_lock(&lpss_iosf_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * Get the status of entire LPSS power island per device basis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * Shutdown both LPSS DMA controllers if and only if all other devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * are already in D3hot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (pmc_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) LPSS_IOSF_PMCSR, value2, mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) LPSS_IOSF_PMCSR, value2, mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) LPSS_IOSF_GPIODEF0, value1, mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) lpss_iosf_d3_entered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) mutex_unlock(&lpss_iosf_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static void lpss_iosf_exit_d3_state(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) LPSS_GPIODEF0_DMA_LLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u32 value2 = LPSS_PMCSR_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u32 mask2 = LPSS_PMCSR_Dx_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mutex_lock(&lpss_iosf_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (!lpss_iosf_d3_entered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) lpss_iosf_d3_entered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) LPSS_IOSF_GPIODEF0, value1, mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) LPSS_IOSF_PMCSR, value2, mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) LPSS_IOSF_PMCSR, value2, mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) mutex_unlock(&lpss_iosf_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static int acpi_lpss_suspend(struct device *dev, bool wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) acpi_lpss_save_ctx(dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = acpi_dev_suspend(dev, wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * This call must be last in the sequence, otherwise PMC will return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * wrong status for devices being about to be powered off. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * lpss_iosf_enter_d3_state() for further information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (acpi_target_system_state() == ACPI_STATE_S0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) lpss_iosf_enter_d3_state();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static int acpi_lpss_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * This call is kept first to be in symmetry with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * acpi_lpss_runtime_suspend() one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) lpss_iosf_exit_d3_state();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ret = acpi_dev_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) acpi_lpss_d3_to_d0_delay(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) acpi_lpss_restore_ctx(dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static int acpi_lpss_do_suspend_late(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (dev_pm_skip_suspend(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = pm_generic_suspend_late(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int acpi_lpss_suspend_late(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (pdata->dev_desc->resume_from_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return acpi_lpss_do_suspend_late(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static int acpi_lpss_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (pdata->dev_desc->resume_from_noirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * The driver's ->suspend_late callback will be invoked by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * acpi_lpss_do_suspend_late(), with the assumption that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * driver really wanted to run that code in ->suspend_noirq, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * it could not run after acpi_dev_suspend() and the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * expected the latter to be called in the "late" phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ret = acpi_lpss_do_suspend_late(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return acpi_subsys_suspend_noirq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static int acpi_lpss_do_resume_early(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int ret = acpi_lpss_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return ret ? ret : pm_generic_resume_early(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static int acpi_lpss_resume_early(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (pdata->dev_desc->resume_from_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (dev_pm_skip_resume(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return acpi_lpss_do_resume_early(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static int acpi_lpss_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* Follow acpi_subsys_resume_noirq(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (dev_pm_skip_resume(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = pm_generic_resume_noirq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (!pdata->dev_desc->resume_from_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * The driver's ->resume_early callback will be invoked by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * acpi_lpss_do_resume_early(), with the assumption that the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * really wanted to run that code in ->resume_noirq, but it could not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * run before acpi_dev_resume() and the driver expected the latter to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * called in the "early" phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return acpi_lpss_do_resume_early(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static int acpi_lpss_do_restore_early(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) int ret = acpi_lpss_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return ret ? ret : pm_generic_restore_early(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static int acpi_lpss_restore_early(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (pdata->dev_desc->resume_from_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return acpi_lpss_do_restore_early(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static int acpi_lpss_restore_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ret = pm_generic_restore_noirq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (!pdata->dev_desc->resume_from_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* This is analogous to what happens in acpi_lpss_resume_noirq(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return acpi_lpss_do_restore_early(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static int acpi_lpss_do_poweroff_late(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int ret = pm_generic_poweroff_late(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static int acpi_lpss_poweroff_late(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (dev_pm_skip_suspend(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (pdata->dev_desc->resume_from_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return acpi_lpss_do_poweroff_late(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static int acpi_lpss_poweroff_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (dev_pm_skip_suspend(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (pdata->dev_desc->resume_from_noirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* This is analogous to the acpi_lpss_suspend_noirq() case. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) int ret = acpi_lpss_do_poweroff_late(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return pm_generic_poweroff_noirq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static int acpi_lpss_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) int ret = pm_generic_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return ret ? ret : acpi_lpss_suspend(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static int acpi_lpss_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) int ret = acpi_lpss_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return ret ? ret : pm_generic_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static struct dev_pm_domain acpi_lpss_pm_domain = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .activate = acpi_lpss_activate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .dismiss = acpi_lpss_dismiss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .prepare = acpi_subsys_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .complete = acpi_subsys_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .suspend = acpi_subsys_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .suspend_late = acpi_lpss_suspend_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .suspend_noirq = acpi_lpss_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .resume_noirq = acpi_lpss_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .resume_early = acpi_lpss_resume_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .freeze = acpi_subsys_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .poweroff = acpi_subsys_poweroff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .poweroff_late = acpi_lpss_poweroff_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .poweroff_noirq = acpi_lpss_poweroff_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .restore_noirq = acpi_lpss_restore_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .restore_early = acpi_lpss_restore_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .runtime_suspend = acpi_lpss_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .runtime_resume = acpi_lpss_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static int acpi_lpss_platform_notify(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct platform_device *pdev = to_platform_device(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct lpss_private_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) const struct acpi_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (!id || !id->driver_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) pdata = acpi_driver_data(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (pdata->mmio_base &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case BUS_NOTIFY_BIND_DRIVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) case BUS_NOTIFY_DRIVER_NOT_BOUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) case BUS_NOTIFY_UNBOUND_DRIVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) dev_pm_domain_set(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) case BUS_NOTIFY_ADD_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (pdata->dev_desc->flags & LPSS_LTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return sysfs_create_group(&pdev->dev.kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) &lpss_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) case BUS_NOTIFY_DEL_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (pdata->dev_desc->flags & LPSS_LTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_pm_domain_set(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static struct notifier_block acpi_lpss_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .notifier_call = acpi_lpss_platform_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static void acpi_lpss_bind(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dev_err(dev, "MMIO size insufficient to access LTR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static void acpi_lpss_unbind(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev->power.set_latency_tolerance = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static struct acpi_scan_handler lpss_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .ids = acpi_lpss_device_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .attach = acpi_lpss_create_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .bind = acpi_lpss_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .unbind = acpi_lpss_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) void __init acpi_lpss_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) const struct x86_cpu_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = lpt_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) id = x86_match_cpu(lpss_cpu_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) acpi_scan_add_handler(&lpss_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static struct acpi_scan_handler lpss_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .ids = acpi_lpss_device_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) void __init acpi_lpss_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) acpi_scan_add_handler(&lpss_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #endif /* CONFIG_X86_INTEL_LPSS */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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