Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * core routines for the asynchronous memory transfer/transform api
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright © 2006, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Dan Williams <dan.j.williams@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *	with architecture considerations by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *	Neil Brown <neilb@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *	Jeff Garzik <jeff@garzik.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/rculist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/async_tx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #ifdef CONFIG_DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static int __init async_tx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	async_dmaengine_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	printk(KERN_INFO "async_tx: api initialized (async)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static void __exit async_tx_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	async_dmaengine_put();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) module_init(async_tx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) module_exit(async_tx_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * __async_tx_find_channel - find a channel to carry out the operation or let
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *	the transaction execute synchronously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @submit: transaction dependency and submission modifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @tx_type: transaction type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) struct dma_chan *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) __async_tx_find_channel(struct async_submit_ctl *submit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			enum dma_transaction_type tx_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	/* see if we can keep the chain on one channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	if (depend_tx &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	    dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return depend_tx->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return async_dma_find_channel(tx_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) EXPORT_SYMBOL_GPL(__async_tx_find_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * async_tx_channel_switch - queue an interrupt descriptor with a dependency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * 	pre-attached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * @depend_tx: the operation that must finish before the new operation runs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * @tx: the new operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct dma_chan *chan = depend_tx->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct dma_device *device = chan->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* first check to see if we can still append to depend_tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	txd_lock(depend_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (txd_parent(depend_tx) && depend_tx->chan == tx->chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		txd_chain(depend_tx, tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		intr_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	txd_unlock(depend_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* attached dependency, flush the parent channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (!intr_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		device->device_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* see if we can schedule an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * otherwise poll for completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (dma_has_cap(DMA_INTERRUPT, device->cap_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		intr_tx = device->device_prep_dma_interrupt(chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		intr_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (intr_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		intr_tx->callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		intr_tx->callback_param = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		/* safe to chain outside the lock since we know we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		 * not submitted yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		txd_chain(intr_tx, tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		/* check if we need to append */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		txd_lock(depend_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (txd_parent(depend_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			txd_chain(depend_tx, intr_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			async_tx_ack(intr_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			intr_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		txd_unlock(depend_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		if (intr_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			txd_clear_parent(intr_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			intr_tx->tx_submit(intr_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			async_tx_ack(intr_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		device->device_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		if (dma_wait_for_async_tx(depend_tx) != DMA_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			panic("%s: DMA error waiting for depend_tx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			      __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		tx->tx_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * submit_disposition - flags for routing an incoming operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * while holding depend_tx->lock we must avoid submitting new operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * to prevent a circular locking dependency with drivers that already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * hold a channel lock when calling async_tx_run_dependencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum submit_disposition {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ASYNC_TX_SUBMITTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ASYNC_TX_CHANNEL_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ASYNC_TX_DIRECT_SUBMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		struct async_submit_ctl *submit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	tx->callback = submit->cb_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	tx->callback_param = submit->cb_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (depend_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		enum submit_disposition s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		/* sanity check the dependency chain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		 * 1/ if ack is already set then we cannot be sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		 * we are referring to the correct operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		 * 2/ dependencies are 1:1 i.e. two transactions can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		 * not depend on the same parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		BUG_ON(async_tx_test_ack(depend_tx) || txd_next(depend_tx) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		       txd_parent(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		/* the lock prevents async_tx_run_dependencies from missing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		 * the setting of ->next when ->parent != NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		txd_lock(depend_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		if (txd_parent(depend_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			/* we have a parent so we can not submit directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			 * if we are staying on the same channel: append
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			 * else: channel switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			if (depend_tx->chan == chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				txd_chain(depend_tx, tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				s = ASYNC_TX_SUBMITTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				s = ASYNC_TX_CHANNEL_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			/* we do not have a parent so we may be able to submit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			 * directly if we are staying on the same channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			if (depend_tx->chan == chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				s = ASYNC_TX_DIRECT_SUBMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				s = ASYNC_TX_CHANNEL_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		txd_unlock(depend_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		switch (s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		case ASYNC_TX_SUBMITTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		case ASYNC_TX_CHANNEL_SWITCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			async_tx_channel_switch(depend_tx, tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		case ASYNC_TX_DIRECT_SUBMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			txd_clear_parent(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			tx->tx_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		txd_clear_parent(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		tx->tx_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (submit->flags & ASYNC_TX_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		async_tx_ack(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (depend_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		async_tx_ack(depend_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) EXPORT_SYMBOL_GPL(async_tx_submit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * async_trigger_callback - schedules the callback function to be run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * @submit: submission and completion parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * honored flags: ASYNC_TX_ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * The callback is run after any dependent operations have completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) async_trigger_callback(struct async_submit_ctl *submit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct dma_device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (depend_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		chan = depend_tx->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		device = chan->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		/* see if we can schedule an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		 * otherwise poll for completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		pr_debug("%s: (async)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		async_tx_submit(chan, tx, submit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		pr_debug("%s: (sync)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		/* wait for any prerequisite operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		async_tx_quiesce(&submit->depend_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		async_tx_sync_epilog(submit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) EXPORT_SYMBOL_GPL(async_trigger_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * async_tx_quiesce - ensure tx is complete and freeable upon return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * @tx - transaction to quiesce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void async_tx_quiesce(struct dma_async_tx_descriptor **tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (*tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		/* if ack is already set then we cannot be sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		 * we are referring to the correct operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		BUG_ON(async_tx_test_ack(*tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		if (dma_wait_for_async_tx(*tx) != DMA_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			panic("%s: DMA error waiting for transaction\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			      __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		async_tx_ack(*tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		*tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) EXPORT_SYMBOL_GPL(async_tx_quiesce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MODULE_AUTHOR("Intel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_LICENSE("GPL");