Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2016 Christoph Hellwig.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/kobject.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/blk-mq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/blk-mq-pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "blk-mq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * blk_mq_pci_map_queues - provide a default queue mapping for PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * @qmap:	CPU to hardware queue map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * @pdev:	PCI device associated with @set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * @offset:	Offset to use for the pci irq vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * This function assumes the PCI device @pdev has at least as many available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * interrupt vectors as @set has queues.  It will then query the vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * corresponding to each queue for it's affinity mask and built queue mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * that maps a queue to the CPUs that have irq affinity for the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int blk_mq_pci_map_queues(struct blk_mq_queue_map *qmap, struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			    int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	const struct cpumask *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	unsigned int queue, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	for (queue = 0; queue < qmap->nr_queues; queue++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		mask = pci_irq_get_affinity(pdev, queue + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		if (!mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			goto fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		for_each_cpu(cpu, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			qmap->mq_map[cpu] = qmap->queue_offset + queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) fallback:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	WARN_ON_ONCE(qmap->nr_queues > 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	blk_mq_clear_mq_map(qmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) EXPORT_SYMBOL_GPL(blk_mq_pci_map_queues);