Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * arch/xtensa/mm/misc.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Miscellaneous assembly functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2001 - 2007 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Chris Zankel	<chris@zankel.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/cacheasm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * clear_page and clear_user_page are the same for non-cache-aliased configs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * clear_page (unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *                    a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) ENTRY(clear_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	movi	a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	__loopi	a2, a7, PAGE_SIZE, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	s32i	a3, a2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	s32i	a3, a2, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	s32i	a3, a2, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	s32i	a3, a2, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	s32i	a3, a2, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	s32i	a3, a2, 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	s32i	a3, a2, 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	s32i	a3, a2, 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	__endla	a2, a7, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) ENDPROC(clear_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * copy_page and copy_user_page are the same for non-cache-aliased configs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * copy_page (void *to, void *from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  *               a2          a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) ENTRY(copy_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	__loopi a2, a4, PAGE_SIZE, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	l32i    a8, a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	l32i    a9, a3, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	s32i    a8, a2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	s32i    a9, a2, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	l32i    a8, a3, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	l32i    a9, a3, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	s32i    a8, a2, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	s32i    a9, a2, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	l32i    a8, a3, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	l32i    a9, a3, 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	s32i    a8, a2, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	s32i    a9, a2, 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	l32i    a8, a3, 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	l32i    a9, a3, 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	s32i    a8, a2, 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	s32i    a9, a2, 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	addi    a2, a2, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	addi    a3, a3, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	__endl  a2, a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) ENDPROC(copy_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * If we have to deal with cache aliasing, we use temporary memory mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * to ensure that the source and destination pages have the same color as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * the virtual address. We use way 0 and 1 for temporary mappings in such cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * The temporary DTLB entries shouldn't be flushed by interrupts, but are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * flushed by preemptive task switches. Special code in the 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * fast_second_level_miss handler re-established the temporary mapping. 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * It requires that the PPNs for the destination and source addresses are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * in a6, and a7, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* TLB miss exceptions are treated special in the following region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ENTRY(__tlbtemp_mapping_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #if (DCACHE_WAY_SIZE > PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * clear_page_alias(void *addr, unsigned long paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  *                     a2              a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ENTRY(clear_page_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* Skip setting up a temporary DTLB if not aliased low page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	movi	a5, PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	movi	a6, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	beqz	a3, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* Setup a temporary DTLB for the addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	addi	a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	mov	a4, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	wdtlb	a6, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 1:	movi	a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	__loopi	a2, a7, PAGE_SIZE, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	s32i	a3, a2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	s32i	a3, a2, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	s32i	a3, a2, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	s32i	a3, a2, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	s32i	a3, a2, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	s32i	a3, a2, 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	s32i	a3, a2, 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	s32i	a3, a2, 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	__endla	a2, a7, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	bnez	a6, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* We need to invalidate the temporary idtlb entry, if any. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 1:	idtlb	a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ENDPROC(clear_page_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * copy_page_alias(void *to, void *from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  *			a2	  a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *                 unsigned long to_paddr, unsigned long from_paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *	        		 a4			 a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ENTRY(copy_page_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* Skip setting up a temporary DTLB for destination if not aliased. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	movi	a6, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	movi	a7, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	beqz	a4, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* Setup a temporary DTLB for destination. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	addi	a6, a4, (PAGE_KERNEL | _PAGE_HW_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	wdtlb	a6, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/* Skip setting up a temporary DTLB for source if not aliased. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 1:	beqz	a5, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* Setup a temporary DTLB for source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	addi	a7, a5, PAGE_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	addi	a8, a3, 1				# way1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	wdtlb	a7, a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 1:	__loopi a2, a4, PAGE_SIZE, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	l32i    a8, a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	l32i    a9, a3, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	s32i    a8, a2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	s32i    a9, a2, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	l32i    a8, a3, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	l32i    a9, a3, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	s32i    a8, a2, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	s32i    a9, a2, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	l32i    a8, a3, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	l32i    a9, a3, 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	s32i    a8, a2, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	s32i    a9, a2, 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	l32i    a8, a3, 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	l32i    a9, a3, 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	s32i    a8, a2, 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	s32i    a9, a2, 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	addi    a2, a2, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	addi    a3, a3, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	__endl  a2, a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/* We need to invalidate any temporary mapping! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	bnez	a6, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	bnez	a7, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 1:	addi	a2, a2, -PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	idtlb	a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	bnez	a7, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 2:	addi	a3, a3, -PAGE_SIZE+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	idtlb	a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ENDPROC(copy_page_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #if (DCACHE_WAY_SIZE > PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  * void __flush_invalidate_dcache_page_alias (addr, phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  *                                             a2    a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ENTRY(__flush_invalidate_dcache_page_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	movi	a7, 0			# required for exception handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	addi	a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	mov	a4, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	wdtlb	a6, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	___flush_invalidate_dcache_page a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	idtlb	a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ENDPROC(__flush_invalidate_dcache_page_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * void __invalidate_dcache_page_alias (addr, phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *                                       a2    a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ENTRY(__invalidate_dcache_page_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	movi	a7, 0			# required for exception handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	addi	a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	mov	a4, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	wdtlb	a6, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	___invalidate_dcache_page a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	idtlb	a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ENDPROC(__invalidate_dcache_page_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ENTRY(__tlbtemp_mapping_itlb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #if (ICACHE_WAY_SIZE > PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ENTRY(__invalidate_icache_page_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	addi	a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	mov	a4, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	witlb	a6, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	___invalidate_icache_page a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	iitlb	a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ENDPROC(__invalidate_icache_page_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* End of special treatment in tlb miss exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ENTRY(__tlbtemp_mapping_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #endif /* CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  * void __invalidate_icache_page(ulong start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ENTRY(__invalidate_icache_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	___invalidate_icache_page a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ENDPROC(__invalidate_icache_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  * void __invalidate_dcache_page(ulong start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ENTRY(__invalidate_dcache_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	___invalidate_dcache_page a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ENDPROC(__invalidate_dcache_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)  * void __flush_invalidate_dcache_page(ulong start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ENTRY(__flush_invalidate_dcache_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	___flush_invalidate_dcache_page a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ENDPROC(__flush_invalidate_dcache_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)  * void __flush_dcache_page(ulong start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ENTRY(__flush_dcache_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	___flush_dcache_page a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ENDPROC(__flush_dcache_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)  * void __invalidate_icache_range(ulong start, ulong size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ENTRY(__invalidate_icache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	___invalidate_icache_range a2 a3 a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ENDPROC(__invalidate_icache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)  * void __flush_invalidate_dcache_range(ulong start, ulong size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ENTRY(__flush_invalidate_dcache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	___flush_invalidate_dcache_range a2 a3 a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ENDPROC(__flush_invalidate_dcache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)  * void _flush_dcache_range(ulong start, ulong size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ENTRY(__flush_dcache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	___flush_dcache_range a2 a3 a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ENDPROC(__flush_dcache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)  * void _invalidate_dcache_range(ulong start, ulong size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ENTRY(__invalidate_dcache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	___invalidate_dcache_range a2 a3 a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ENDPROC(__invalidate_dcache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)  * void _invalidate_icache_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ENTRY(__invalidate_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	___invalidate_icache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ENDPROC(__invalidate_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)  * void _flush_invalidate_dcache_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ENTRY(__flush_invalidate_dcache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	___flush_invalidate_dcache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ENDPROC(__flush_invalidate_dcache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)  * void _invalidate_dcache_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ENTRY(__invalidate_dcache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	___invalidate_dcache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	dsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	abi_ret_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ENDPROC(__invalidate_dcache_all)