^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/xtensa/mm/cache.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2001-2006 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Chris Zankel <chris@zankel.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Joe Taylor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Marc Gauthier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/swap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pagemap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/bootparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/tlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * The kernel provides one architecture bit PG_arch_1 in the page flags that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * can be used for cache coherency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * I$-D$ coherency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * The Xtensa architecture doesn't keep the instruction cache coherent with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * the data cache. We use the architecture bit to indicate if the caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * are coherent. The kernel clears this bit whenever a page is added to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * page cache. At that time, the caches might not be in sync. We, therefore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * define this flag as 'clean' if set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * D-cache aliasing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * With cache aliasing, we have to always flush the cache when pages are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * unmapped (see tlb_start_vma(). So, we use this flag to indicate a dirty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #if (DCACHE_WAY_SIZE > PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline void kmap_invalidate_coherent(struct page *page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long vaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (!DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long kvaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!PageHighMem(page)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) kvaddr = (unsigned long)page_to_virt(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __invalidate_dcache_page(kvaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) kvaddr = TLBTEMP_BASE_1 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (page_to_phys(page) & DCACHE_ALIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __invalidate_dcache_page_alias(kvaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) page_to_phys(page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static inline void *coherent_kvaddr(struct page *page, unsigned long base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long vaddr, unsigned long *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (PageHighMem(page) || !DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *paddr = page_to_phys(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return (void *)(base + (vaddr & DCACHE_ALIAS_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *paddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return page_to_virt(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void clear_user_highpage(struct page *page, unsigned long vaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) kmap_invalidate_coherent(page, vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) set_bit(PG_arch_1, &page->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clear_page_alias(kvaddr, paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) EXPORT_SYMBOL(clear_user_highpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void copy_user_highpage(struct page *dst, struct page *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned long vaddr, struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long dst_paddr, src_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) &dst_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) &src_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) kmap_invalidate_coherent(dst, vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) set_bit(PG_arch_1, &dst->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) EXPORT_SYMBOL(copy_user_highpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Any time the kernel writes to a user page cache page, or it is about to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * read from a page cache page this routine is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void flush_dcache_page(struct page *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct address_space *mapping = page_mapping_file(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * If we have a mapping but the page is not mapped to user-space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * yet, we simply mark this page dirty and defer flushing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * caches until update_mmu().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (mapping && !mapping_mapped(mapping)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!test_bit(PG_arch_1, &page->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) set_bit(PG_arch_1, &page->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long phys = page_to_phys(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long temp = page->index << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned long virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Flush the page in kernel space and user space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Note that we can omit that step if aliasing is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * an issue, but we do have to synchronize I$ and D$
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * if we have a mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!alias && !mapping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __flush_invalidate_dcache_page_alias(virt, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __flush_invalidate_dcache_page_alias(virt, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (mapping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __invalidate_icache_page_alias(virt, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* There shouldn't be an entry in the cache for this page anymore. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) EXPORT_SYMBOL(flush_dcache_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * For now, flush the whole cache. FIXME??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void local_flush_cache_range(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __flush_invalidate_dcache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __invalidate_icache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) EXPORT_SYMBOL(local_flush_cache_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Remove any entry in the cache for this page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Note that this function is only called for user pages, so use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * alias versions of the cache flush functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void local_flush_cache_page(struct vm_area_struct *vma, unsigned long address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long pfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Note that we have to use the 'alias' address to avoid multi-hit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long phys = page_to_phys(pfn_to_page(pfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __flush_invalidate_dcache_page_alias(virt, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __invalidate_icache_page_alias(virt, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) EXPORT_SYMBOL(local_flush_cache_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned long pfn = pte_pfn(*ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!pfn_valid(pfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) page = pfn_to_page(pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Invalidate old entry in TLBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) flush_tlb_page(vma, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #if (DCACHE_WAY_SIZE > PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned long phys = page_to_phys(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __flush_invalidate_dcache_page_alias(tmp, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __flush_invalidate_dcache_page_alias(tmp, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) __invalidate_icache_page_alias(tmp, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clear_bit(PG_arch_1, &page->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) && (vma->vm_flags & VM_EXEC) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned long paddr = (unsigned long)kmap_atomic(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __flush_dcache_page(paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __invalidate_icache_page(paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) set_bit(PG_arch_1, &page->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) kunmap_atomic((void *)paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * access_process_vm() has called get_user_pages(), which has done a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * flush_dcache_page() on the page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #if (DCACHE_WAY_SIZE > PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long vaddr, void *dst, const void *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned long phys = page_to_phys(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Flush and invalidate user page if aliased. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (alias) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __flush_invalidate_dcache_page_alias(t, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Copy data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) memcpy(dst, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Flush and invalidate kernel page if aliased and synchronize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * data and instruction caches for executable pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (alias) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __flush_invalidate_dcache_range((unsigned long) dst, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if ((vma->vm_flags & VM_EXEC) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __invalidate_icache_page_alias(t, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } else if ((vma->vm_flags & VM_EXEC) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) __flush_dcache_range((unsigned long)dst,len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) __invalidate_icache_range((unsigned long) dst, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long vaddr, void *dst, const void *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned long phys = page_to_phys(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Flush user page if aliased.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * (Note: a simply flush would be sufficient)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (alias) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) __flush_invalidate_dcache_page_alias(t, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) memcpy(dst, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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