^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/xtensa/lib/pci-auto.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * PCI autoconfiguration library
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2001 - 2005 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Chris Zankel <zankel@tensilica.com, cez@zankel.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Based on work from Matt Porter <mporter@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Setting up a PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * pci_ctrl->first_busno = <first bus number (0)>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * pci_ctrl->last_busno = <last bus number (0xff)>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * pci_ctrl->ops = <PCI config operations>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * pci_ctrl->map_irq = <function to return the interrupt number for a device>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * pci_ctrl->io_space.start = <IO space start address (PCI view)>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * pci_ctrl->io_space.end = <IO space end address (PCI view)>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * pci_ctrl->io_space.base = <IO space offset: address 0 from CPU space>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * pci_ctrl->mem_space.start = <MEM space start address (PCI view)>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * pci_ctrl->mem_space.end = <MEM space end address (PCI view)>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * pci_ctrl->mem_space.base = <MEM space offset: address 0 from CPU space>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * pcibios_init_resource(&pci_ctrl->io_resource, <IO space start>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * <IO space end>, IORESOURCE_IO, "PCI host bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * pcibios_init_resource(&pci_ctrl->mem_resources[0], <MEM space start>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * <MEM space end>, IORESOURCE_MEM, "PCI host bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * pci_ctrl->last_busno = pciauto_bus_scan(pci_ctrl,pci_ctrl->first_busno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int pciauto_upper_iospc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int pciauto_upper_memspc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct pci_dev pciauto_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct pci_bus pciauto_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Helper functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Initialize the bars of a PCI device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pciauto_setup_bars(struct pci_dev *dev, int bar_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int bar_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int bar, bar_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int *upper_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int found_mem64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) for (bar = PCI_BASE_ADDRESS_0, bar_nr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bar <= bar_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bar+=4, bar_nr++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Tickle the BAR and get the size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pci_write_config_dword(dev, bar, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pci_read_config_dword(dev, bar, &bar_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* If BAR is not implemented go to the next BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (!bar_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Check the BAR type and set our address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (bar_size & PCI_BASE_ADDRESS_SPACE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bar_size &= PCI_BASE_ADDRESS_IO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) upper_limit = &pciauto_upper_iospc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pr_debug("PCI Autoconfig: BAR %d, I/O, ", bar_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if ((bar_size & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PCI_BASE_ADDRESS_MEM_TYPE_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) found_mem64 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bar_size &= PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) upper_limit = &pciauto_upper_memspc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pr_debug("PCI Autoconfig: BAR %d, Mem, ", bar_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Allocate a base address (bar_size is negative!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *upper_limit = (*upper_limit + bar_size) & bar_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Write it out and update our limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pci_write_config_dword(dev, bar, *upper_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * If we are a 64-bit decoder then increment to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * upper 32 bits of the bar and force it to locate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * in the lower 4GB of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (found_mem64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pci_write_config_dword(dev, (bar+=4), 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pr_debug("size=0x%x, address=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ~bar_size + 1, *upper_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Initialize the interrupt number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pciauto_setup_irq(struct pci_controller* pci_ctrl,struct pci_dev *dev,int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Fix illegal pin numbers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (pin == 0 || pin > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pin = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (pci_ctrl->map_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) irq = pci_ctrl->map_irq(dev, PCI_SLOT(devfn), pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (irq == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_debug("PCI Autoconfig: Interrupt %d, pin %d\n", irq, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pciauto_prescan_setup_bridge(struct pci_dev *dev, int current_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int sub_bus, int *iosave, int *memsave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Configure bus number registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pci_write_config_byte(dev, PCI_PRIMARY_BUS, current_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pci_write_config_byte(dev, PCI_SECONDARY_BUS, sub_bus + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Round memory allocator to 1MB boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pciauto_upper_memspc &= ~(0x100000 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *memsave = pciauto_upper_memspc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Round I/O allocator to 4KB boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pciauto_upper_iospc &= ~(0x1000 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *iosave = pciauto_upper_iospc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Set up memory and I/O filter limits, assume 32-bit I/O space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pci_write_config_word(dev, PCI_MEMORY_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pci_write_config_byte(dev, PCI_IO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pciauto_postscan_setup_bridge(struct pci_dev *dev, int current_bus, int sub_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int *iosave, int *memsave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int cmdstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Configure bus number registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, sub_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Round memory allocator to 1MB boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * If no space used, allocate minimum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pciauto_upper_memspc &= ~(0x100000 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (*memsave == pciauto_upper_memspc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pciauto_upper_memspc -= 0x00100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pci_write_config_word(dev, PCI_MEMORY_BASE, pciauto_upper_memspc >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Allocate 1MB for pre-fretch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pciauto_upper_memspc -= 0x100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pci_write_config_word(dev, PCI_PREF_MEMORY_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pciauto_upper_memspc >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Round I/O allocator to 4KB boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pciauto_upper_iospc &= ~(0x1000 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (*iosave == pciauto_upper_iospc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pciauto_upper_iospc -= 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pci_write_config_byte(dev, PCI_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) (pciauto_upper_iospc & 0x0000f000) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pciauto_upper_iospc >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Enable memory and I/O accesses, enable bus master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pci_read_config_dword(dev, PCI_COMMAND, &cmdstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pci_write_config_dword(dev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cmdstat |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PCI_COMMAND_IO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PCI_COMMAND_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Scan the current PCI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int sub_bus, pci_devfn, pci_class, cmdstat, found_multi=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned short vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned char header_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct pci_dev *dev = &pciauto_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pciauto_dev.bus = &pciauto_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pciauto_dev.sysdata = pci_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pciauto_bus.ops = pci_ctrl->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Fetch our I/O and memory space upper boundaries used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * to allocated base addresses on this pci_controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (current_bus == pci_ctrl->first_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pciauto_upper_iospc = pci_ctrl->io_resource.end + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pciauto_upper_memspc = pci_ctrl->mem_resources[0].end + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sub_bus = current_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Skip our host bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if ((current_bus == pci_ctrl->first_busno) && (pci_devfn == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (PCI_FUNC(pci_devfn) && !found_multi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pciauto_bus.number = current_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pciauto_dev.devfn = pci_devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* If config space read fails from this device, move on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!PCI_FUNC(pci_devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) found_multi = header_type & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pci_read_config_word(dev, PCI_VENDOR_ID, &vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (vid == 0xffff || vid == 0x0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) found_multi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pci_read_config_dword(dev, PCI_CLASS_REVISION, &pci_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int iosave, memsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pr_debug("PCI Autoconfig: Found P2P bridge, device %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PCI_SLOT(pci_devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Allocate PCI I/O and/or memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pciauto_setup_bars(dev, PCI_BASE_ADDRESS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pciauto_prescan_setup_bridge(dev, current_bus, sub_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) &iosave, &memsave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) sub_bus = pciauto_bus_scan(pci_ctrl, sub_bus+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pciauto_postscan_setup_bridge(dev, current_bus, sub_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) &iosave, &memsave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pciauto_bus.number = current_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Found a peripheral, enable some standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pci_read_config_dword(dev, PCI_COMMAND, &cmdstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pci_write_config_dword(dev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cmdstat |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PCI_COMMAND_IO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PCI_COMMAND_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Allocate PCI I/O and/or memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pr_debug("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pciauto_setup_bars(dev, PCI_BASE_ADDRESS_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pciauto_setup_irq(pci_ctrl, dev, pci_devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return sub_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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