Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * arch/xtensa/kernel/vmlinux.lds.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Xtensa linker script
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2001 - 2008 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Chris Zankel <chris@zankel.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define RO_EXCEPTION_TABLE_ALIGN	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm-generic/vmlinux.lds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/vectors.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) OUTPUT_ARCH(xtensa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) ENTRY(_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #ifdef __XTENSA_EB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) jiffies = jiffies_64 + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) jiffies = jiffies_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Note: In the following macros, it would be nice to specify only the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)    vector name and section kind and construct "sym" and "section" using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)    CPP concatenation, but that does not work reliably.  Concatenating a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)    string with "." produces an invalid token.  CPP will not print a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)    warning because it thinks this is an assembly file, but it leaves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)    them as multiple tokens and there may or may not be whitespace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)    between them.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* Macro for a relocation entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RELOCATE_ENTRY(sym, section)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	LONG(sym ## _start);			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	LONG(sym ## _end);			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	LONG(LOADADDR(section))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #if !defined(CONFIG_VECTORS_ADDR) && XCHAL_HAVE_VECBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MERGED_VECTORS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MERGED_VECTORS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * Macro to define a section for a vector. When MERGED_VECTORS is 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * code for every vector is located with other init data. At startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * time head.S copies code for every vector to its final position according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * to description recorded in the corresponding RELOCATE_ENTRY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SECTION_VECTOR4(sym, section, addr, prevsec)			    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)   section addr : AT(((LOADADDR(prevsec) + SIZEOF(prevsec)) + 3) & ~ 3)      \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)   {									    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)     . = ALIGN(4);							    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)     sym ## _start = ABSOLUTE(.);		 			    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)     *(section)								    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)     sym ## _end = ABSOLUTE(.);						    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)   }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SECTION_VECTOR2(section, addr)					    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)   . = addr;								    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)   *(section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *  Mapping of input sections to output sections when linking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) SECTIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)   . = KERNELOFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)   /* .text section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)   _text = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)   _stext = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)   .text :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)   {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)     /* The HEAD_TEXT section must be the first section! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)     HEAD_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #if MERGED_VECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)     . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)     _vecbase = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)     SECTION_VECTOR2 (.WindowVectors.text, WINDOW_VECTORS_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #if XCHAL_EXCM_LEVEL >= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)     SECTION_VECTOR2 (.Level2InterruptVector.text, INTLEVEL2_VECTOR_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #if XCHAL_EXCM_LEVEL >= 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)     SECTION_VECTOR2 (.Level3InterruptVector.text, INTLEVEL3_VECTOR_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #if XCHAL_EXCM_LEVEL >= 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)     SECTION_VECTOR2 (.Level4InterruptVector.text, INTLEVEL4_VECTOR_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #if XCHAL_EXCM_LEVEL >= 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)     SECTION_VECTOR2 (.Level5InterruptVector.text, INTLEVEL5_VECTOR_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #if XCHAL_EXCM_LEVEL >= 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)     SECTION_VECTOR2 (.Level6InterruptVector.text, INTLEVEL6_VECTOR_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)     SECTION_VECTOR2 (.DebugInterruptVector.text, DEBUG_VECTOR_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)     SECTION_VECTOR2 (.KernelExceptionVector.text, KERNEL_VECTOR_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)     SECTION_VECTOR2 (.UserExceptionVector.text, USER_VECTOR_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)     SECTION_VECTOR2 (.DoubleExceptionVector.text, DOUBLEEXC_VECTOR_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)     *(.exception.text)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)     IRQENTRY_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)     SOFTIRQENTRY_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)     ENTRY_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)     TEXT_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)     SCHED_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)     CPUIDLE_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)     LOCK_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)     *(.fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)   }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)   _etext = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)   PROVIDE (etext = .);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)   . = ALIGN(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)   RO_DATA(4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)   /* Data section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)   INIT_TEXT_SECTION(PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)   _sdata = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)   RW_DATA(XCHAL_ICACHE_LINESIZE, PAGE_SIZE, THREAD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)   _edata = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)   /* Initialization code and data: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)   . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)   __init_begin = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)   INIT_TEXT_SECTION(PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)   .init.data :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)   {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)     INIT_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)   }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)   .init.rodata :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)   {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)     . = ALIGN(0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)     __tagtable_begin = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)     *(.taglist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)     __tagtable_end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)     . = ALIGN(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)     __boot_reloc_table_start = ABSOLUTE(.);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #if !MERGED_VECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)     RELOCATE_ENTRY(_WindowVectors_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		   .WindowVectors.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #if XCHAL_EXCM_LEVEL >= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)     RELOCATE_ENTRY(_Level2InterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		   .Level2InterruptVector.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #if XCHAL_EXCM_LEVEL >= 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)     RELOCATE_ENTRY(_Level3InterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		   .Level3InterruptVector.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #if XCHAL_EXCM_LEVEL >= 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)     RELOCATE_ENTRY(_Level4InterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		   .Level4InterruptVector.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #if XCHAL_EXCM_LEVEL >= 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)     RELOCATE_ENTRY(_Level5InterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		   .Level5InterruptVector.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #if XCHAL_EXCM_LEVEL >= 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)     RELOCATE_ENTRY(_Level6InterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		   .Level6InterruptVector.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)     RELOCATE_ENTRY(_KernelExceptionVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		   .KernelExceptionVector.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)     RELOCATE_ENTRY(_UserExceptionVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		   .UserExceptionVector.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)     RELOCATE_ENTRY(_DoubleExceptionVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		   .DoubleExceptionVector.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)     RELOCATE_ENTRY(_DebugInterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		   .DebugInterruptVector.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)     RELOCATE_ENTRY(_exception_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		   .exception.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)     RELOCATE_ENTRY(_xip_data, .data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)     RELOCATE_ENTRY(_xip_init_data, .init.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #if defined(CONFIG_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)     RELOCATE_ENTRY(_SecondaryResetVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		   .SecondaryResetVector.text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)     __boot_reloc_table_end = ABSOLUTE(.) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)     INIT_SETUP(XCHAL_ICACHE_LINESIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)     INIT_CALLS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)     CON_INITCALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)     INIT_RAM_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)   }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)   PERCPU_SECTION(XCHAL_ICACHE_LINESIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)   /* We need this dummy segment here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)   . = ALIGN(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)   .dummy : { LONG(0) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #undef LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define LAST	.dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #if !MERGED_VECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)   /* The vectors are relocated to the real position at startup time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)   SECTION_VECTOR4 (_WindowVectors_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		  .WindowVectors.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		  WINDOW_VECTORS_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		  .dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)   SECTION_VECTOR4 (_DebugInterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		  .DebugInterruptVector.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		  DEBUG_VECTOR_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		  .WindowVectors.text)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #undef LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define LAST	.DebugInterruptVector.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #if XCHAL_EXCM_LEVEL >= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)   SECTION_VECTOR4 (_Level2InterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		  .Level2InterruptVector.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		  INTLEVEL2_VECTOR_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		  LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) # undef LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) # define LAST	.Level2InterruptVector.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #if XCHAL_EXCM_LEVEL >= 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)   SECTION_VECTOR4 (_Level3InterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		  .Level3InterruptVector.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		  INTLEVEL3_VECTOR_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		  LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) # undef LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) # define LAST	.Level3InterruptVector.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #if XCHAL_EXCM_LEVEL >= 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)   SECTION_VECTOR4 (_Level4InterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		  .Level4InterruptVector.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		  INTLEVEL4_VECTOR_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		  LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) # undef LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) # define LAST	.Level4InterruptVector.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #if XCHAL_EXCM_LEVEL >= 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)   SECTION_VECTOR4 (_Level5InterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		  .Level5InterruptVector.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		  INTLEVEL5_VECTOR_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		  LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) # undef LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) # define LAST	.Level5InterruptVector.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #if XCHAL_EXCM_LEVEL >= 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)   SECTION_VECTOR4 (_Level6InterruptVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		  .Level6InterruptVector.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		  INTLEVEL6_VECTOR_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		  LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) # undef LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) # define LAST	.Level6InterruptVector.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)   SECTION_VECTOR4 (_KernelExceptionVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		  .KernelExceptionVector.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		  KERNEL_VECTOR_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		  LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #undef LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)   SECTION_VECTOR4 (_UserExceptionVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		  .UserExceptionVector.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		  USER_VECTOR_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		  .KernelExceptionVector.text)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)   SECTION_VECTOR4 (_DoubleExceptionVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		  .DoubleExceptionVector.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		  DOUBLEEXC_VECTOR_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		  .UserExceptionVector.text)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define LAST .DoubleExceptionVector.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #if defined(CONFIG_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)   SECTION_VECTOR4 (_SecondaryResetVector_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		  .SecondaryResetVector.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		  RESET_VECTOR1_VADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		  LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #undef LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define LAST .SecondaryResetVector.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #if !MERGED_VECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)   SECTION_VECTOR4 (_exception_text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		  .exception.text,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		  ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		  LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #undef LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define LAST .exception.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)   . = (LOADADDR(LAST) + SIZEOF(LAST) + 3) & ~ 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)   .dummy1 : AT(ADDR(.dummy1)) { LONG(0) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)   . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #ifndef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)   __init_end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)   BSS_SECTION(0, 8192, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)   _end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)   . = CONFIG_XIP_DATA_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)   _xip_start = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #undef LOAD_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define LOAD_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)   (CONFIG_XIP_DATA_ADDR - (LOADADDR(.dummy1) + SIZEOF(.dummy1) + 3) & ~ 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)   _xip_data_start = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)   _sdata = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)   RW_DATA(XCHAL_ICACHE_LINESIZE, PAGE_SIZE, THREAD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)   _edata = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)   _xip_data_end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)   /* Initialization data: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)   STRUCT_ALIGN();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)   _xip_init_data_start = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)   __init_begin = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)   .init.data :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)   {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)     INIT_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)   }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)   _xip_init_data_end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)   __init_end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)   BSS_SECTION(0, 8192, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)   _xip_end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #undef LOAD_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)   DWARF_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)   .xt.prop 0 : { KEEP(*(.xt.prop .xt.prop.* .gnu.linkonce.prop.*)) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)   .xt.insn 0 : { KEEP(*(.xt.insn .xt.insn.* .gnu.linkonce.x*)) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)   .xt.lit  0 : { KEEP(*(.xt.lit  .xt.lit.*  .gnu.linkonce.p*)) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)   /* Sections to be discarded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)   DISCARDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }