^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/xtensa/kernel/setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1995 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2001 - 2005 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Chris Zankel <chris@zankel.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Kevin Chea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/screen_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) # include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) # include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/bootparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/kasan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/sysmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct screen_info screen_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .orig_x = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .orig_y = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .orig_video_cols = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .orig_video_lines = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .orig_video_isVGA = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .orig_video_points = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef CONFIG_BLK_DEV_INITRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern unsigned long initrd_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) extern unsigned long initrd_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) extern int initrd_below_start_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifdef CONFIG_USE_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void *dtb_start = __dtb_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern unsigned long loops_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Command line specified as configuration option. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static char __initdata command_line[COMMAND_LINE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef CONFIG_CMDLINE_BOOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifdef CONFIG_PARSE_BOOTPARAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Boot parameter parsing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * The Xtensa port uses a list of variable-sized tags to pass data to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * to be recognised. The list is terminated with a zero-sized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * BP_TAG_LAST tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) typedef struct tagtable {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int (*parse)(const bp_tag_t*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } tagtable_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __section(".taglist") __attribute__((used)) = { tag, fn }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* parse current tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int __init parse_tag_mem(const bp_tag_t *tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (mi->type != MEMORY_TYPE_CONVENTIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return memblock_add(mi->start, mi->end - mi->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __tagtable(BP_TAG_MEMORY, parse_tag_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef CONFIG_BLK_DEV_INITRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int __init parse_tag_initrd(const bp_tag_t* tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) initrd_start = (unsigned long)__va(mi->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) initrd_end = (unsigned long)__va(mi->end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __tagtable(BP_TAG_INITRD, parse_tag_initrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif /* CONFIG_BLK_DEV_INITRD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #ifdef CONFIG_USE_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int __init parse_tag_fdt(const bp_tag_t *tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dtb_start = __va(tag->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __tagtable(BP_TAG_FDT, parse_tag_fdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif /* CONFIG_USE_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int __init parse_tag_cmdline(const bp_tag_t* tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int __init parse_bootparam(const bp_tag_t* tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) extern tagtable_t __tagtable_begin, __tagtable_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) tagtable_t *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Boot parameters must start with a BP_TAG_FIRST tag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (tag->id != BP_TAG_FIRST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pr_warn("Invalid boot parameters!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Parse all tags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) while (tag != NULL && tag->id != BP_TAG_LAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (tag->id == t->tag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) t->parse(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (t == &__tagtable_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pr_warn("Ignoring tag 0x%08x\n", tag->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int __init parse_bootparam(const bp_tag_t *tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pr_info("Ignoring boot parameters at %p\n", tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #ifdef CONFIG_USE_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) EXPORT_SYMBOL(xtensa_kio_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int depth, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const __be32 *ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (depth > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (!of_flat_dt_is_compatible(node, "simple-bus"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ranges = of_get_flat_dt_prop(node, "ranges", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!ranges)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* round down to nearest 256MB boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) xtensa_kio_paddr &= 0xf0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) init_kio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int depth, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void __init early_init_devtree(void *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) early_init_dt_scan(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) of_scan_flat_dt(xtensa_dt_io_area, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!command_line[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #endif /* CONFIG_USE_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Initialize architecture. (Early stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void __init init_arch(bp_tag_t *bp_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Initialize MMU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) init_mmu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Initialize initial KASAN shadow map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) kasan_early_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Parse boot parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (bp_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) parse_bootparam(bp_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #ifdef CONFIG_USE_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) early_init_devtree(dtb_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #ifdef CONFIG_CMDLINE_BOOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!command_line[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Early hook for platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) platform_init(bp_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Initialize system. Setup memory and reserve regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) extern char _end[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) extern char _stext[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) extern char _WindowVectors_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) extern char _WindowVectors_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) extern char _DebugInterruptVector_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) extern char _DebugInterruptVector_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) extern char _KernelExceptionVector_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) extern char _KernelExceptionVector_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) extern char _UserExceptionVector_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) extern char _UserExceptionVector_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) extern char _DoubleExceptionVector_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) extern char _DoubleExceptionVector_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) extern char _exception_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) extern char _exception_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #if XCHAL_EXCM_LEVEL >= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) extern char _Level2InterruptVector_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) extern char _Level2InterruptVector_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #if XCHAL_EXCM_LEVEL >= 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) extern char _Level3InterruptVector_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) extern char _Level3InterruptVector_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #if XCHAL_EXCM_LEVEL >= 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) extern char _Level4InterruptVector_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) extern char _Level4InterruptVector_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #if XCHAL_EXCM_LEVEL >= 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) extern char _Level5InterruptVector_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) extern char _Level5InterruptVector_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #if XCHAL_EXCM_LEVEL >= 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) extern char _Level6InterruptVector_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) extern char _Level6InterruptVector_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) extern char _SecondaryResetVector_text_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) extern char _SecondaryResetVector_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) extern char _xip_start[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) extern char _xip_end[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static inline int __init_memblock mem_reserve(unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return memblock_reserve(start, end - start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void __init setup_arch(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pr_info("config ID: %08x:%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pr_info("built for config ID: %08x:%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *cmdline_p = command_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) platform_setup(cmdline_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Reserve some memory regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #ifdef CONFIG_BLK_DEV_INITRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (initrd_start < initrd_end &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) !mem_reserve(__pa(initrd_start), __pa(initrd_end)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) initrd_below_start_ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) initrd_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mem_reserve(__pa(_stext), __pa(_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mem_reserve(__pa(_xip_start), __pa(_xip_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #ifdef CONFIG_VECTORS_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mem_reserve(__pa(&_WindowVectors_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) __pa(&_WindowVectors_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mem_reserve(__pa(&_DebugInterruptVector_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) __pa(&_DebugInterruptVector_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mem_reserve(__pa(&_KernelExceptionVector_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) __pa(&_KernelExceptionVector_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mem_reserve(__pa(&_UserExceptionVector_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) __pa(&_UserExceptionVector_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) mem_reserve(__pa(&_DoubleExceptionVector_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __pa(&_DoubleExceptionVector_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mem_reserve(__pa(&_exception_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __pa(&_exception_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #if XCHAL_EXCM_LEVEL >= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mem_reserve(__pa(&_Level2InterruptVector_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __pa(&_Level2InterruptVector_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #if XCHAL_EXCM_LEVEL >= 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) mem_reserve(__pa(&_Level3InterruptVector_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) __pa(&_Level3InterruptVector_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #if XCHAL_EXCM_LEVEL >= 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mem_reserve(__pa(&_Level4InterruptVector_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) __pa(&_Level4InterruptVector_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #if XCHAL_EXCM_LEVEL >= 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mem_reserve(__pa(&_Level5InterruptVector_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) __pa(&_Level5InterruptVector_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #if XCHAL_EXCM_LEVEL >= 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mem_reserve(__pa(&_Level6InterruptVector_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) __pa(&_Level6InterruptVector_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #endif /* CONFIG_VECTORS_ADDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mem_reserve(__pa(&_SecondaryResetVector_text_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __pa(&_SecondaryResetVector_text_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) parse_early_param();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) bootmem_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) kasan_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unflatten_and_copy_device_tree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) smp_init_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) paging_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) zones_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #ifdef CONFIG_VT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) # if defined(CONFIG_VGA_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) conswitchp = &vga_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static DEFINE_PER_CPU(struct cpu, cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int __init topology_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) for_each_possible_cpu(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct cpu *cpu = &per_cpu(cpu_data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cpu->hotpluggable = !!i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) register_cpu(cpu, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) subsys_initcall(topology_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) void cpu_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * be flushed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * Way 4 is not currently used by linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Way 5 shall be flushed and way 6 shall be set to identity mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * on MMUv3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) local_flush_tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) invalidate_page_directory();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #if XCHAL_HAVE_SPANNING_WAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* MMU v3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned long vaddr = (unsigned long)cpu_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned long paddr = __pa(vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned long tmpaddr = vaddr + SZ_512M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long tmp0, tmp1, tmp2, tmp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Find a place for the temporary mapping. It must not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * in the same 512MB region with vaddr or paddr, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * there may be multihit exception either on entry to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * temporary mapping, or on entry to the identity mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * (512MB is the biggest page size supported by TLB.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) tmpaddr += SZ_512M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Invalidate mapping in the selected temporary area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) invalidate_itlb_entry(itlb_probe(tmpaddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Map two consecutive pages starting at the physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * of this function to the temporary mapping area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) write_itlb_entry(__pte((paddr & PAGE_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) _PAGE_HW_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) _PAGE_HW_EXEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) _PAGE_CA_BYPASS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) tmpaddr & PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) _PAGE_HW_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) _PAGE_HW_EXEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) _PAGE_CA_BYPASS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (tmpaddr & PAGE_MASK) + PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Reinitialize TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) __asm__ __volatile__ ("movi %0, 1f\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "movi %3, 2f\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "add %0, %0, %4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "add %3, %3, %5\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "jx %0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * No literal, data or stack access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * below this point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) "1:\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Initialize *tlbcfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) "movi %0, 0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "wsr %0, itlbcfg\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "wsr %0, dtlbcfg\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Invalidate TLB way 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "movi %0, 4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) "movi %1, 5\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "1:\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "iitlb %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "idtlb %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "add %1, %1, %6\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "addi %0, %0, -1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "bnez %0, 1b\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Initialize TLB way 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "movi %0, 7\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) "addi %1, %9, 3\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) "addi %2, %9, 6\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "1:\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "witlb %1, %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "wdtlb %1, %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "add %1, %1, %7\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) "add %2, %2, %7\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) "addi %0, %0, -1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) "bnez %0, 1b\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "isync\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Jump to identity mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "jx %3\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "2:\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Complete way 6 initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "witlb %1, %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "wdtlb %1, %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Invalidate temporary mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "sub %0, %9, %7\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "iitlb %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "add %0, %0, %8\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "iitlb %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "=&a"(tmp3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) : "a"(tmpaddr - vaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "a"(paddr - vaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) "a"(SZ_128M), "a"(SZ_512M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) "a"(PAGE_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) "a"((tmpaddr + SZ_512M) & PAGE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __asm__ __volatile__ ("movi a2, 0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "wsr a2, icountlevel\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) "movi a2, 0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "wsr a2, icount\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #if XCHAL_NUM_IBREAK > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "wsr a2, ibreakenable\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #if XCHAL_HAVE_LOOPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) "wsr a2, lcount\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) "movi a2, 0x1f\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "wsr a2, ps\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "isync\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "jx %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) : "a" (XCHAL_RESET_VECTOR_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) : "a2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for (;;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) void machine_restart(char * cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) platform_restart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) void machine_halt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) platform_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) void machine_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) platform_power_off();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * Display some core information through /proc/cpuinfo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) c_show(struct seq_file *f, void *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* high-level stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) seq_printf(f, "CPU count\t: %u\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) "CPU list\t: %*pbl\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) "vendor_id\t: Tensilica\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) "core ID\t\t: " XCHAL_CORE_ID "\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "build ID\t: 0x%x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "config ID\t: %08x:%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "byte order\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "cpu MHz\t\t: %lu.%02lu\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "bogomips\t: %lu.%02lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) num_online_cpus(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) cpumask_pr_args(cpu_online_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) XCHAL_BUILD_UNIQUE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) XCHAL_HAVE_BE ? "big" : "little",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ccount_freq/1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) (ccount_freq/10000) % 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) loops_per_jiffy/(500000/HZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) (loops_per_jiffy/(5000/HZ)) % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) seq_puts(f, "flags\t\t: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #if XCHAL_HAVE_NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "nmi "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #if XCHAL_HAVE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "debug "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) # if XCHAL_HAVE_OCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "ocd "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #if XCHAL_HAVE_DENSITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "density "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #if XCHAL_HAVE_BOOLEANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "boolean "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #if XCHAL_HAVE_LOOPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "loop "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #if XCHAL_HAVE_NSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "nsa "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #if XCHAL_HAVE_MINMAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "minmax "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #if XCHAL_HAVE_SEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "sext "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #if XCHAL_HAVE_CLAMPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "clamps "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #if XCHAL_HAVE_MAC16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "mac16 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #if XCHAL_HAVE_MUL16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) "mul16 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #if XCHAL_HAVE_MUL32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) "mul32 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #if XCHAL_HAVE_MUL32_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "mul32h "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #if XCHAL_HAVE_FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) "fpu "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #if XCHAL_HAVE_S32C1I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "s32c1i "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #if XCHAL_HAVE_EXCLUSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) "exclusive "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) seq_printf(f,"physical aregs\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "misc regs\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "ibreak\t\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "dbreak\t\t: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) XCHAL_NUM_AREGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) XCHAL_NUM_MISC_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) XCHAL_NUM_IBREAK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) XCHAL_NUM_DBREAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) seq_printf(f,"num ints\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) "ext ints\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) "int levels\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "timers\t\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "debug level\t: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) XCHAL_NUM_INTERRUPTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) XCHAL_NUM_EXTINTERRUPTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) XCHAL_NUM_INTLEVELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) XCHAL_NUM_TIMERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) XCHAL_DEBUGLEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) seq_printf(f,"icache line size: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "icache ways\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "icache size\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "icache flags\t: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #if XCHAL_ICACHE_LINE_LOCKABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) "lock "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "dcache line size: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "dcache ways\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "dcache size\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "dcache flags\t: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #if XCHAL_DCACHE_IS_WRITEBACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "writeback "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #if XCHAL_DCACHE_LINE_LOCKABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) "lock "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) XCHAL_ICACHE_LINESIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) XCHAL_ICACHE_WAYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) XCHAL_ICACHE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) XCHAL_DCACHE_LINESIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) XCHAL_DCACHE_WAYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) XCHAL_DCACHE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * We show only CPU #0 info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) c_start(struct seq_file *f, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return (*pos == 0) ? (void *)1 : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) c_next(struct seq_file *f, void *v, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ++*pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return c_start(f, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) c_stop(struct seq_file *f, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) const struct seq_operations cpuinfo_op =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .start = c_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .next = c_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .stop = c_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .show = c_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #endif /* CONFIG_PROC_FS */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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