Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Xtensa Performance Monitor Module driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * See Tensilica Debug User's Guide for PMU registers documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2015 Cadence Design Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/stacktrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* Global control/status for all perf counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define XTENSA_PMU_PMG			0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Perf counter values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define XTENSA_PMU_PM(i)		(0x1080 + (i) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* Perf counter control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define XTENSA_PMU_PMCTRL(i)		(0x1100 + (i) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* Perf counter status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define XTENSA_PMU_PMSTAT(i)		(0x1180 + (i) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define XTENSA_PMU_PMG_PMEN		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define XTENSA_PMU_COUNTER_MASK		0xffffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define XTENSA_PMU_COUNTER_MAX		0x7fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define XTENSA_PMU_PMCTRL_INTEN		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define XTENSA_PMU_PMCTRL_KRNLCNT	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define XTENSA_PMU_PMCTRL_TRACELEVEL	0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define XTENSA_PMU_PMCTRL_SELECT_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define XTENSA_PMU_PMCTRL_SELECT	0x00001f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define XTENSA_PMU_PMCTRL_MASK_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define XTENSA_PMU_PMCTRL_MASK		0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define XTENSA_PMU_MASK(select, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	(((select) << XTENSA_PMU_PMCTRL_SELECT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	 ((mask) << XTENSA_PMU_PMCTRL_MASK_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	 XTENSA_PMU_PMCTRL_TRACELEVEL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	 XTENSA_PMU_PMCTRL_INTEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define XTENSA_PMU_PMSTAT_OVFL		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define XTENSA_PMU_PMSTAT_INTASRT	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct xtensa_pmu_events {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/* Array of events currently on this core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct perf_event *event[XCHAL_NUM_PERF_COUNTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/* Bitmap of used hardware counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned long used_mask[BITS_TO_LONGS(XCHAL_NUM_PERF_COUNTERS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static DEFINE_PER_CPU(struct xtensa_pmu_events, xtensa_pmu_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static const u32 xtensa_hw_ctl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	[PERF_COUNT_HW_CPU_CYCLES]		= XTENSA_PMU_MASK(0, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	[PERF_COUNT_HW_INSTRUCTIONS]		= XTENSA_PMU_MASK(2, 0xffff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	[PERF_COUNT_HW_CACHE_REFERENCES]	= XTENSA_PMU_MASK(10, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	[PERF_COUNT_HW_CACHE_MISSES]		= XTENSA_PMU_MASK(12, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* Taken and non-taken branches + taken loop ends */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= XTENSA_PMU_MASK(2, 0x490),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* Instruction-related + other global stall cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= XTENSA_PMU_MASK(4, 0x1ff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* Data-related global stall cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= XTENSA_PMU_MASK(3, 0x1ff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define C(_x) PERF_COUNT_HW_CACHE_##_x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static const u32 xtensa_cache_ctl[][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	[C(L1D)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		[C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			[C(RESULT_ACCESS)]	= XTENSA_PMU_MASK(10, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			[C(RESULT_MISS)]	= XTENSA_PMU_MASK(10, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		[C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			[C(RESULT_ACCESS)]	= XTENSA_PMU_MASK(11, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			[C(RESULT_MISS)]	= XTENSA_PMU_MASK(11, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	[C(L1I)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		[C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			[C(RESULT_ACCESS)]	= XTENSA_PMU_MASK(8, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			[C(RESULT_MISS)]	= XTENSA_PMU_MASK(8, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	[C(DTLB)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		[C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			[C(RESULT_ACCESS)]	= XTENSA_PMU_MASK(9, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			[C(RESULT_MISS)]	= XTENSA_PMU_MASK(9, 0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	[C(ITLB)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		[C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			[C(RESULT_ACCESS)]	= XTENSA_PMU_MASK(7, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			[C(RESULT_MISS)]	= XTENSA_PMU_MASK(7, 0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int xtensa_pmu_cache_event(u64 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned int cache_type, cache_op, cache_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	cache_type = (config >>  0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	cache_op = (config >>  8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	cache_result = (config >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (cache_type >= ARRAY_SIZE(xtensa_cache_ctl) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	    cache_op >= C(OP_MAX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	    cache_result >= C(RESULT_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ret = xtensa_cache_ctl[cache_type][cache_op][cache_result];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline uint32_t xtensa_pmu_read_counter(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return get_er(XTENSA_PMU_PM(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline void xtensa_pmu_write_counter(int idx, uint32_t v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	set_er(v, XTENSA_PMU_PM(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void xtensa_perf_event_update(struct perf_event *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				     struct hw_perf_event *hwc, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	uint64_t prev_raw_count, new_raw_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	int64_t delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		prev_raw_count = local64_read(&hwc->prev_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		new_raw_count = xtensa_pmu_read_counter(event->hw.idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				 new_raw_count) != prev_raw_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	delta = (new_raw_count - prev_raw_count) & XTENSA_PMU_COUNTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	local64_add(delta, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	local64_sub(delta, &hwc->period_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static bool xtensa_perf_event_set_period(struct perf_event *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 					 struct hw_perf_event *hwc, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	bool rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	s64 left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (!is_sampling_event(event)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		left = XTENSA_PMU_COUNTER_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		s64 period = hwc->sample_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		left = local64_read(&hwc->period_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		if (left <= -period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			left = period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			local64_set(&hwc->period_left, left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			hwc->last_period = period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			rc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		} else if (left <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			left += period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			local64_set(&hwc->period_left, left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			hwc->last_period = period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			rc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		if (left > XTENSA_PMU_COUNTER_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			left = XTENSA_PMU_COUNTER_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	local64_set(&hwc->prev_count, -left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	xtensa_pmu_write_counter(idx, -left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void xtensa_pmu_enable(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	set_er(get_er(XTENSA_PMU_PMG) | XTENSA_PMU_PMG_PMEN, XTENSA_PMU_PMG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void xtensa_pmu_disable(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	set_er(get_er(XTENSA_PMU_PMG) & ~XTENSA_PMU_PMG_PMEN, XTENSA_PMU_PMG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int xtensa_pmu_event_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	switch (event->attr.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	case PERF_TYPE_HARDWARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		if (event->attr.config >= ARRAY_SIZE(xtensa_hw_ctl) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		    xtensa_hw_ctl[event->attr.config] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		event->hw.config = xtensa_hw_ctl[event->attr.config];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	case PERF_TYPE_HW_CACHE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		ret = xtensa_pmu_cache_event(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		event->hw.config = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case PERF_TYPE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		/* Not 'previous counter' select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		if ((event->attr.config & XTENSA_PMU_PMCTRL_SELECT) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		    (1 << XTENSA_PMU_PMCTRL_SELECT_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		event->hw.config = (event->attr.config &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				    (XTENSA_PMU_PMCTRL_KRNLCNT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				     XTENSA_PMU_PMCTRL_TRACELEVEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				     XTENSA_PMU_PMCTRL_SELECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				     XTENSA_PMU_PMCTRL_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			XTENSA_PMU_PMCTRL_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * Starts/Stops a counter present on the PMU. The PMI handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  * should stop the counter when perf_event_overflow() returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * !0. ->start() will be used to continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void xtensa_pmu_start(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int idx = hwc->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (WARN_ON_ONCE(idx == -1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (flags & PERF_EF_RELOAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		xtensa_perf_event_set_period(event, hwc, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	hwc->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	set_er(hwc->config, XTENSA_PMU_PMCTRL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void xtensa_pmu_stop(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	int idx = hwc->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (!(hwc->state & PERF_HES_STOPPED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		set_er(0, XTENSA_PMU_PMCTRL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		set_er(get_er(XTENSA_PMU_PMSTAT(idx)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		       XTENSA_PMU_PMSTAT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		hwc->state |= PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if ((flags & PERF_EF_UPDATE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	    !(event->hw.state & PERF_HES_UPTODATE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		xtensa_perf_event_update(event, &event->hw, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		event->hw.state |= PERF_HES_UPTODATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  * Adds/Removes a counter to/from the PMU, can be done inside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  * a transaction, see the ->*_txn() methods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int xtensa_pmu_add(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct xtensa_pmu_events *ev = this_cpu_ptr(&xtensa_pmu_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int idx = hwc->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (__test_and_set_bit(idx, ev->used_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		idx = find_first_zero_bit(ev->used_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 					  XCHAL_NUM_PERF_COUNTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		if (idx == XCHAL_NUM_PERF_COUNTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		__set_bit(idx, ev->used_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		hwc->idx = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	ev->event[idx] = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (flags & PERF_EF_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		xtensa_pmu_start(event, PERF_EF_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void xtensa_pmu_del(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct xtensa_pmu_events *ev = this_cpu_ptr(&xtensa_pmu_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	xtensa_pmu_stop(event, PERF_EF_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	__clear_bit(event->hw.idx, ev->used_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void xtensa_pmu_read(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	xtensa_perf_event_update(event, &event->hw, event->hw.idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int callchain_trace(struct stackframe *frame, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct perf_callchain_entry_ctx *entry = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	perf_callchain_store(entry, frame->pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			   struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	xtensa_backtrace_kernel(regs, entry->max_stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 				callchain_trace, NULL, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			 struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	xtensa_backtrace_user(regs, entry->max_stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			      callchain_trace, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) void perf_event_print_debug(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	pr_info("CPU#%d: PMG: 0x%08lx\n", smp_processor_id(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		get_er(XTENSA_PMU_PMG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	for (i = 0; i < XCHAL_NUM_PERF_COUNTERS; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		pr_info("PM%d: 0x%08lx, PMCTRL%d: 0x%08lx, PMSTAT%d: 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			i, get_er(XTENSA_PMU_PM(i)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			i, get_er(XTENSA_PMU_PMCTRL(i)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			i, get_er(XTENSA_PMU_PMSTAT(i)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) irqreturn_t xtensa_pmu_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	irqreturn_t rc = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	struct xtensa_pmu_events *ev = this_cpu_ptr(&xtensa_pmu_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	for_each_set_bit(i, ev->used_mask, XCHAL_NUM_PERF_COUNTERS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		uint32_t v = get_er(XTENSA_PMU_PMSTAT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		struct perf_event *event = ev->event[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		u64 last_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		if (!(v & XTENSA_PMU_PMSTAT_OVFL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		set_er(v, XTENSA_PMU_PMSTAT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		xtensa_perf_event_update(event, hwc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		last_period = hwc->last_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		if (xtensa_perf_event_set_period(event, hwc, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			struct perf_sample_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			struct pt_regs *regs = get_irq_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			perf_sample_data_init(&data, 0, last_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			if (perf_event_overflow(event, &data, regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 				xtensa_pmu_stop(event, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		rc = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct pmu xtensa_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	.pmu_enable = xtensa_pmu_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	.pmu_disable = xtensa_pmu_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.event_init = xtensa_pmu_event_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.add = xtensa_pmu_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.del = xtensa_pmu_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.start = xtensa_pmu_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.stop = xtensa_pmu_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.read = xtensa_pmu_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int xtensa_pmu_setup(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	set_er(0, XTENSA_PMU_PMG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	for (i = 0; i < XCHAL_NUM_PERF_COUNTERS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		set_er(0, XTENSA_PMU_PMCTRL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		set_er(get_er(XTENSA_PMU_PMSTAT(i)), XTENSA_PMU_PMSTAT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int __init xtensa_pmu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	int irq = irq_create_mapping(NULL, XCHAL_PROFILING_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	ret = cpuhp_setup_state(CPUHP_AP_PERF_XTENSA_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 				"perf/xtensa:starting", xtensa_pmu_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 				NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		pr_err("xtensa_pmu: failed to register CPU-hotplug.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #if XTENSA_FAKE_NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	ret = request_irq(irq, xtensa_pmu_irq_handler, IRQF_PERCPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 			  "pmu", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	ret = perf_pmu_register(&xtensa_pmu, "cpu", PERF_TYPE_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		free_irq(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) early_initcall(xtensa_pmu_init);