^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Xtensa Secondary Processors startup code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2001 - 2013 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Joe Taylor <joe@tensilica.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Chris Zankel <chris@zankel.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Pete Delaney <piet@tensilica.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cacheasm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/initialize_mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mxregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .section .SecondaryResetVector.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ENTRY(_SecondaryResetVector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) _j _SetupOCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .begin no-absolute-literals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .literal_position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) _SetupOCD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * xt-gdb to single step via DEBUG exceptions received directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * by ocd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) movi a1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) movi a0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) wsr a1, windowstart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) wsr a0, windowbase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) rsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) movi a1, LOCKLEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) wsr a1, ps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) rsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) _SetupMMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) initialize_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Start Secondary Processors with NULL pointer to boot params.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) movi a2, 0 # a2 == NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) movi a3, _startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) jx a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .end no-absolute-literals