Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Xtensa hardware breakpoints/watchpoints handling functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2016 Cadence Design Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/hw_breakpoint.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* Breakpoint currently in use for each IBREAKA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[XCHAL_NUM_IBREAK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* Watchpoint currently in use for each DBREAKA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[XCHAL_NUM_DBREAK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) int hw_breakpoint_slots(int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	case TYPE_INST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		return XCHAL_NUM_IBREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	case TYPE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		return XCHAL_NUM_DBREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		pr_warn("unknown slot type: %d\n", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned long va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	va = hw->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	len = hw->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * Construct an arch_hw_breakpoint from a perf_event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) int hw_breakpoint_arch_parse(struct perf_event *bp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			     const struct perf_event_attr *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			     struct arch_hw_breakpoint *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/* Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	switch (attr->bp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	case HW_BREAKPOINT_X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		hw->type = XTENSA_BREAKPOINT_EXECUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	case HW_BREAKPOINT_R:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		hw->type = XTENSA_BREAKPOINT_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case HW_BREAKPOINT_W:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		hw->type = XTENSA_BREAKPOINT_STORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	case HW_BREAKPOINT_RW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		hw->type = XTENSA_BREAKPOINT_LOAD | XTENSA_BREAKPOINT_STORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* Len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	hw->len = attr->bp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (hw->len < 1 || hw->len > 64 || !is_power_of_2(hw->len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/* Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	hw->address = attr->bp_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (hw->address & (hw->len - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				    unsigned long val, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void xtensa_wsr(unsigned long v, u8 sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* We don't have indexed wsr and creating instruction dynamically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * doesn't seem worth it given how small XCHAL_NUM_IBREAK and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * XCHAL_NUM_DBREAK are. Thus the switch. In case build breaks here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * the switch below needs to be extended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	BUILD_BUG_ON(XCHAL_NUM_IBREAK > 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	BUILD_BUG_ON(XCHAL_NUM_DBREAK > 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	switch (sr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #if XCHAL_NUM_IBREAK > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	case SREG_IBREAKA + 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		xtensa_set_sr(v, SREG_IBREAKA + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #if XCHAL_NUM_IBREAK > 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	case SREG_IBREAKA + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		xtensa_set_sr(v, SREG_IBREAKA + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #if XCHAL_NUM_DBREAK > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	case SREG_DBREAKA + 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		xtensa_set_sr(v, SREG_DBREAKA + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case SREG_DBREAKC + 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		xtensa_set_sr(v, SREG_DBREAKC + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #if XCHAL_NUM_DBREAK > 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case SREG_DBREAKA + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		xtensa_set_sr(v, SREG_DBREAKA + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case SREG_DBREAKC + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		xtensa_set_sr(v, SREG_DBREAKC + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int alloc_slot(struct perf_event **slot, size_t n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		      struct perf_event *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	for (i = 0; i < n; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		if (!slot[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			slot[i] = bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void set_ibreak_regs(int reg, struct perf_event *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned long ibreakenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	xtensa_wsr(info->address, SREG_IBREAKA + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	xtensa_set_sr(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void set_dbreak_regs(int reg, struct perf_event *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	unsigned long dbreakc = DBREAKC_MASK_MASK & -info->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (info->type & XTENSA_BREAKPOINT_LOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		dbreakc |= DBREAKC_LOAD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (info->type & XTENSA_BREAKPOINT_STORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		dbreakc |= DBREAKC_STOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	xtensa_wsr(info->address, SREG_DBREAKA + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	xtensa_wsr(dbreakc, SREG_DBREAKC + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int arch_install_hw_breakpoint(struct perf_event *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (counter_arch_bp(bp)->type == XTENSA_BREAKPOINT_EXECUTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		/* Breakpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		i = alloc_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		set_ibreak_regs(i, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		/* Watchpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		i = alloc_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		set_dbreak_regs(i, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int free_slot(struct perf_event **slot, size_t n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		     struct perf_event *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	for (i = 0; i < n; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		if (slot[i] == bp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			slot[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void arch_uninstall_hw_breakpoint(struct perf_event *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (info->type == XTENSA_BREAKPOINT_EXECUTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		unsigned long ibreakenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		/* Breakpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		i = free_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		if (i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			xtensa_set_sr(ibreakenable & ~(1 << i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 				      SREG_IBREAKENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		/* Watchpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		i = free_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		if (i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			xtensa_wsr(0, SREG_DBREAKC + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void hw_breakpoint_pmu_read(struct perf_event *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct thread_struct *t = &tsk->thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		if (t->ptrace_bp[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			unregister_hw_breakpoint(t->ptrace_bp[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			t->ptrace_bp[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		if (t->ptrace_wp[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			unregister_hw_breakpoint(t->ptrace_wp[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			t->ptrace_wp[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * Set ptrace breakpoint pointers to zero for this task.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * This is required in order to prevent child processes from unregistering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  * breakpoints held by their parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	memset(tsk->thread.ptrace_bp, 0, sizeof(tsk->thread.ptrace_bp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	memset(tsk->thread.ptrace_wp, 0, sizeof(tsk->thread.ptrace_wp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void restore_dbreak(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		struct perf_event *bp = this_cpu_ptr(wp_on_reg)[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		if (bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			set_dbreak_regs(i, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	clear_thread_flag(TIF_DB_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int check_hw_breakpoint(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (regs->debugcause & BIT(DEBUGCAUSE_IBREAK_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		struct perf_event **bp = this_cpu_ptr(bp_on_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			if (bp[i] && !bp[i]->attr.disabled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			    regs->pc == bp[i]->attr.bp_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 				perf_bp_event(bp[i], regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	} else if (regs->debugcause & BIT(DEBUGCAUSE_DBREAK_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		struct perf_event **bp = this_cpu_ptr(wp_on_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		int dbnum = (regs->debugcause & DEBUGCAUSE_DBNUM_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			DEBUGCAUSE_DBNUM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		if (dbnum < XCHAL_NUM_DBREAK && bp[dbnum]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			if (user_mode(regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 				perf_bp_event(bp[dbnum], regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				set_thread_flag(TIF_DB_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				xtensa_wsr(0, SREG_DBREAKC + dbnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			WARN_ONCE(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 				  "Wrong/unconfigured DBNUM reported in DEBUGCAUSE: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				  dbnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }