Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * arch/xtensa/kernel/head.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Xtensa Processor startup code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2001 - 2008 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Chris Zankel <chris@zankel.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Kevin Chea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/cacheasm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/initialize_mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/mxregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * This module contains the entry code for kernel images. It performs the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * minimal setup needed to call the generic C routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * Prerequisites:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * - The kernel image has been loaded to the actual address where it was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *   compiled to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * - a2 contains either 0 or a pointer to a list of boot parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *   (see setup.c for more details)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *  _start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *  The bootloader passes a pointer to a list of boot parameters in a2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* The first bytes of the kernel image must be an instruction, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	 * manually allocate and define the literal constant we need for a jx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 * instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	__HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.begin	no-absolute-literals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) ENTRY(_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	wsr     a2, excsave1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	_j	_SetupOCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.literal_position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) _SetupOCD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * xt-gdb to single step via DEBUG exceptions received directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 * by ocd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	movi	a1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	movi	a0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	wsr	a1, windowstart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	wsr	a0, windowbase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	rsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	movi	a1, LOCKLEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	wsr	a1, ps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	rsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.global _SetupMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) _SetupMMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	Offset = _SetupMMU - _start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	initialize_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	rsr	a2, excsave1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	movi	a3, XCHAL_KSEG_PADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	bltu	a2, a3, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	sub	a2, a2, a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	movi	a3, XCHAL_KSEG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	bgeu	a2, a3, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	movi	a3, XCHAL_KSEG_CACHED_VADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	add	a2, a2, a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	wsr	a2, excsave1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	movi	a0, _startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	jx	a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ENDPROC(_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.end	no-absolute-literals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	__REF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.literal_position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ENTRY(_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* Set a0 to 0 for the remaining initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	movi	a0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #if XCHAL_HAVE_VECBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	movi    a2, VECBASE_VADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	wsr	a2, vecbase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/* Clear debugging registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #if XCHAL_HAVE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #if XCHAL_NUM_IBREAK > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	wsr	a0, ibreakenable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	wsr	a0, icount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	movi	a1, 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	wsr	a0, icountlevel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.set	_index, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.rept	XCHAL_NUM_DBREAK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	wsr	a0, SREG_DBREAKC + _index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.set	_index, _index + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* Clear CCOUNT (not really necessary, but nice) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	wsr	a0, ccount	# not really necessary, but nice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* Disable zero-loops. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #if XCHAL_HAVE_LOOPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	wsr	a0, lcount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* Disable all timers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.set	_index, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.rept	XCHAL_NUM_TIMERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	wsr	a0, SREG_CCOMPARE + _index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.set	_index, _index + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* Interrupt initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	movi	a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	wsr	a0, intenable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	wsr	a2, intclear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* Disable coprocessors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #if XCHAL_HAVE_CP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	wsr	a0, cpenable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/*  Initialize the caches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 *  a2, a3 are just working registers (clobbered).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #if XCHAL_DCACHE_LINE_LOCKABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	___unlock_dcache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #if XCHAL_ICACHE_LINE_LOCKABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	___unlock_icache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	___invalidate_dcache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	___invalidate_icache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	initialize_cacheattr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #ifdef CONFIG_HAVE_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	movi	a2, CCON	# MX External Register to Configure Cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	movi	a3, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	wer	a3, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Setup stack and enable window exceptions (keep irqs disabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	movi	a1, start_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	l32i	a1, a1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	movi	a2, PS_WOE_MASK | LOCKLEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 					# WOE=1, INTLEVEL=LOCKLEVEL, UM=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	wsr	a2, ps			# (enable reg-windows; progmode stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	rsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * Notice that we assume with SMP that cores have PRID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 * supported by the cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	rsr	a2, prid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	bnez	a2, .Lboot_secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif  /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* Unpack data sections
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 * The linker script used to build the Linux kernel image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * creates a table located at __boot_reloc_table_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 * that contans the information what data needs to be unpacked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * Uses a2-a7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	movi	a2, __boot_reloc_table_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	movi	a3, __boot_reloc_table_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 1:	beq	a2, a3, 3f	# no more entries?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	l32i	a4, a2, 0	# start destination (in RAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	l32i	a5, a2, 4	# end desination (in RAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	l32i	a6, a2, 8	# start source (in ROM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	addi	a2, a2, 12	# next entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	beq	a4, a5, 1b	# skip, empty entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	beq	a4, a6, 1b	# skip, source and dest. are the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 2:	l32i	a7, a6, 0	# load word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	addi	a6, a6, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	s32i	a7, a4, 0	# store word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	addi	a4, a4, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	bltu	a4, a5, 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	j	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* All code and initialized data segments have been copied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * Now clear the BSS segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	movi	a2, __bss_start	# start of BSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	movi	a3, __bss_stop	# end of BSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	__loopt	a2, a3, a4, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	s32i	a0, a2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	__endla	a2, a3, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #if XCHAL_DCACHE_IS_WRITEBACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* After unpacking, flush the writeback cache to memory so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 * instructions/data are available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	___flush_dcache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	memw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	___invalidate_icache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	/* Setup bootstrap CPU stack in XIP kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	movi	a1, start_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	l32i	a1, a1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	movi	a6, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	xsr	a6, excsave1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/* init_arch kick-starts the linux kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	call4	init_arch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	call4	start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) should_never_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	j	should_never_return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .Lboot_secondary:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	movi	a2, cpu_start_ccount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	memw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	l32i	a3, a2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	beqi	a3, 0, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	movi	a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	s32i	a3, a2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	memw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	l32i	a3, a2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	beqi	a3, 0, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	wsr	a3, ccount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	movi	a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	s32i	a3, a2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	memw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	movi	a6, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	wsr	a6, excsave1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	call4	secondary_start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	j	should_never_return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #endif  /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ENDPROC(_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ENTRY(cpu_restart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #if XCHAL_DCACHE_IS_WRITEBACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	___flush_invalidate_dcache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	___invalidate_dcache_all a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	memw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	movi	a2, CCON	# MX External Register to Configure Cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	movi	a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	wer	a3, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	extw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	rsr	a0, prid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	neg	a2, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	movi	a3, cpu_start_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	memw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	s32i	a2, a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #if XCHAL_DCACHE_IS_WRITEBACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	dhwbi	a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	memw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	l32i	a2, a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	dhi	a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	bne	a2, a0, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	 * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	 * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	 * xt-gdb to single step via DEBUG exceptions received directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	 * by ocd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	movi	a1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	movi	a0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	wsr	a1, windowstart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	wsr	a0, windowbase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	rsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	movi	a1, LOCKLEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	wsr	a1, ps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	rsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	j	_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ENDPROC(cpu_restart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif  /* CONFIG_HOTPLUG_CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)  * DATA section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	__REFDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.align  4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ENTRY(start_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.long	init_thread_union + KERNEL_STACK_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)  * BSS section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) __PAGE_ALIGNED_BSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ENTRY(swapper_pg_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	.fill	PAGE_SIZE, 1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) END(swapper_pg_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ENTRY(empty_zero_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	.fill	PAGE_SIZE, 1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) END(empty_zero_page)